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BS EN 61131-9:2013:2014 Edition

BS EN 61131-9:2013:2014 Edition

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Programmable controllers – Single-drop digital communication interface for small sensors and actuators (SDCI)

Published By Publication Date Number of Pages
BSI 2014 264
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IEC 61131-9:2013 specifies a single-drop digital communication interface technology for small sensors and actuators SDCI (commonly known as IO-Link), which extends the traditional digital input and digital output interfaces as defined in IEC 61131-2 towards a point-to-point communication link. This technology enables the transfer of parameters to Devices and the delivery of diagnostic information from the Devices to the automation system.

PDF Catalog

PDF Pages PDF Title
7 English
CONTENTS
19 INTRODUCTION
21 1 Scope
2 Normative references
22 3 Terms, definitions, symbols, abbreviated terms and conventions
3.1 Terms and definitions
26 3.2 Symbols and abbreviated terms
28 3.3 Conventions
3.3.1 General
3.3.2 Service parameters
29 3.3.3 Service procedures
3.3.4 Service attributes
3.3.5 Figures
3.3.6 Transmission octet order
Figures
Figure 1 – Example of a confirmed service
30 3.3.7 Behavioral descriptions
4 Overview of SDCI (IO-LinkTM)
4.1 Purpose of technology
Figure 2 – Memory storage and transmission order for WORD based data types
Figure 3 – SDCI compatibility with IEC 611312
31 4.2 Positioning within the automation hierarchy
Figure 4 – Domain of the SDCI technology within the automation hierarchy
32 4.3 Wiring, connectors and power
4.4 Communication features of SDCI
Figure 5 – Generic Device model for SDCI (Master’s view)
33 Figure 6 – Relationship between nature of data and transmission types
34 4.5 Role of a Master
Figure 7 – Object transfer at the application layer level (AL)
35 4.6 SDCI configuration
4.7 Mapping to fieldbuses
4.8 Standard structure
Figure 8 – Logical structure of Master and Device
36 5 Physical Layer (PL)
5.1 General
5.1.1 Basics
5.1.2 Topology
Figure 9 – Three wire connection system
37 5.2 Physical layer services
5.2.1 Overview
Figure 10 – Topology of SDCI
Figure 11 – Physical layer (Master)
38 5.2.2 PL services
Figure 12 – Physical layer (Device)
Tables
Table 1 – Service assignments of Master and Device
Table 2 – PL_SetMode
39 Table 3 – PL_WakeUp
Table 4 – PL_Transfer
40 5.3 Transmitter/Receiver
5.3.1 Description method
5.3.2 Electrical requirements
Figure 13 – Line driver reference schematics
Figure 14 – Receiver reference schematics
41 Figure 15 – Reference schematics for SDCI 3-wire connection system
Figure 16 – Voltage level definitions
42 Figure 17 – Switching thresholds
Table 5 – Electric characteristics of a receiver
Table 6 – Electric characteristics of a Master port
43 Table 7 – Electric characteristics of a Device
44 5.3.3 Timing requirements
Figure 18 – Format of an SDCI UART frame
45 Figure 19 – Eye diagram for the ‘H’ and ‘L’ detection
Figure 20 – Eye diagram for the correct detection of a UART frame
46 Table 8 – Dynamic characteristics of the transmission
47 5.4 Power supply
5.4.1 Power supply options
Figure 21 – Wake-up request
Table 9 – Wake-up request characteristics
48 5.4.2 Power-on requirements
5.5 Medium
5.5.1 Connectors
Figure 22 – Power-on timing for Power1
Table 10 – Power-on timing
49 Figure 23 – Pin layout front view
Table 11 – Pin assignments
50 5.5.2 Cable
Figure 24 – Class A and B port definitions
Figure 25 – Reference schematic for effective line capacitance and loop resistance
Table 12 – Cable characteristics
51 6 Standard Input and Output (SIO)
7 Data link layer (DL)
7.1 General
Table 13 – Cable conductor assignments
52 Figure 26 – Structure and services of the data link layer (Master)
Figure 27 – Structure and services of the data link layer (Device)
53 7.2 Data link layer services
7.2.1 DL-B services
Table 14 – Service assignments within Master and Device
54 Table 15 – DL_ReadParam
Table 16 – DL_WriteParam
55 Table 17 – DL_Read
56 Table 18 – DL_Write
57 Table 19 – DL_ISDUTransport
58 Table 20 – DL_ISDUAbort
Table 21 – DL_PDOutputUpdate
59 Table 22 – DL_PDOutputTransport
60 Table 23 – DL_PDInputUpdate
Table 24 – DL_PDInputTransport
61 Table 25 – DL_PDCycle
Table 26 – DL_SetMode
62 Table 27 – DL_Mode
63 Table 28 – DL_Event
Table 29 – DL_EventConf
64 7.2.2 DL-A services
Table 30 – DL_EventTrigger
Table 31 – DL_Control
65 Table 32 – DL-A services within Master and Device
Table 33 – OD
66 Table 34 – PD
67 Table 35 – EventFlag
68 Table 36 – PDInStatus
Table 37 – MHInfo
69 7.3 Data link layer protocol
7.3.1 Overview
Table 38 – ODTrig
Table 39 – PDTrig
70 7.3.2 DL-mode handler
Figure 28 – State machines of the data link layer
Figure 29 – Example of an attempt to establish communication
71 Figure 30 – Failed attempt to establish communication
Figure 31 – Retry strategy to establish communication
72 Figure 32 – Fallback procedure
Table 40 – Wake-up procedure and retry characteristics
73 Figure 33 – State machine of the Master DL-mode handler
Table 41 – Fallback timing characteristics
74 Figure 34 – Submachine 1 to establish communication
Table 42 – State transition tables of the Master DL-mode handler
76 Figure 35 – State machine of the Device DL-mode handler
77 Table 43 – State transition tables of the Device DL-mode handler
78 7.3.3 Message handler
Figure 36 – SDCI message sequences
79 Figure 37 – Overview of M-sequence types
80 Figure 38 – State machine of the Master message handler
81 Figure 39 – Submachine “Response 3” of the message handler
Figure 40 – Submachine “Response 8” of the message handler
Figure 41 – Submachine “Response 15” of the message handler
82 Table 44 – State transition table of the Master message handler
84 Figure 42 – State machine of the Device message handler
85 7.3.4 Process Data handler
Table 45 – State transition tables of the Device message handler
86 Figure 43 – Interleave mode for the segmented transmission of Process Data
Figure 44 – State machine of the Master Process Data handler
87 Table 46 – State transition tables of the Master Process Data handler
88 7.3.5 On-request Data handler
Figure 45 – State machine of the Device Process Data handler
Table 47 – State transition tables of the Device Process Data handler
89 Figure 46 – State machine of the Master On-request Data handler
Table 48 – State transition tables of the Master On-request Data handler
90 Figure 47 – State machine of the Device On-request Data handler
91 7.3.6 ISDU handler
Figure 48 – Structure of the ISDU
Table 49 – State transition tables of the Device On-request Data handler
92 Table 50 – FlowCTRL definitions
93 Figure 49 – State machine of the Master ISDU handler
Table 51 – State transition tables of the Master ISDU handler
94 Figure 50 – State machine of the Device ISDU handler
95 7.3.7 Command handler
Table 52 – State transition tables of the Device ISDU handler
96 Figure 51 – State machine of the Master command handler
Table 53 – Control codes
Table 54 – State transition tables of the Master command handler
97 Figure 52 – State machine of the Device command handler
Table 55 – State transition tables of the Device command handler
98 7.3.8 Event handler
Table 56 – Event memory
99 Figure 53 – State machine of the Master Event handler
Table 57 – State transition tables of the Master Event handler
100 Figure 54 – State machine of the Device Event handler
Table 58 – State transition tables of the Device Event handler
101 8 Application layer (AL)
8.1 General
Figure 55 – Structure and services of the application layer (Master)
102 8.2 Application layer services
8.2.1 AL services within Master and Device
Figure 56 – Structure and services of the application layer (Device)
Table 59 – AL services within Master and Device
103 8.2.2 AL Services
Table 60 – AL_Read
104 Table 61 – AL_Write
105 Table 62 – AL_Abort
Table 63 – AL_GetInput
106 Table 64 – AL_NewInput
107 Table 65 – AL_SetInput
Table 66 – AL_PDCycle
108 Table 67 – AL_GetOutput
Table 68 – AL_NewOutput
109 Table 69 – AL_SetOutput
110 Table 70 – AL_Event
111 8.3 Application layer protocol
8.3.1 Overview
8.3.2 On-request Data transfer
Table 71 – AL_Control
112 Figure 57 – OD state machine of the Master AL
Table 72 – States and transitions for the OD state machine of the Master AL
113 Figure 58 – OD state machine of the Device AL
114 Table 73 – States and transitions for the OD state machine of the Device AL
115 Figure 59 – Sequence diagram for the transmission of On-request Data
116 Figure 60 – Sequence diagram for On-request Data in case of errors
Figure 61 – Sequence diagram for On-request Data in case of timeout
117 8.3.3 Event processing
Figure 62 – Event state machine of the Master AL
Table 74 – State and transitions of the Event state machine of the Master AL
118 Figure 63 – Event state machine of the Device AL
Table 75 – State and transitions of the Event state machine of the Device AL
119 Figure 64 – Single Event scheduling
120 8.3.4 Process Data cycles
Figure 65 – Sequence diagram for output Process Data
121 9 System management (SM)
9.1 General
9.2 System management of the Master
9.2.1 Overview
Figure 66 – Sequence diagram for input Process Data
122 Figure 67 – Structure and services of the Master system management
123 9.2.2 SM Master services
Figure 68 – Sequence chart of the use case “port x setup”
124 Table 76 – SM services within the Master
Table 77 – SM_SetPortConfig
125 Table 78 – Definition of the InspectionLevel (IL)
126 Table 79 – Definitions of the Target Modes
Table 80 – SM_GetPortConfig
127 Table 81 – SM_PortMode
128 9.2.3 SM Master protocol
Table 82 – SM_Operate
129 Figure 69 – Main state machine of the Master system management
130 Table 83 – State transition tables of the Master system management
131 Figure 70 – SM Master submachine CheckCompatibility_1
Table 84 – State transition tables of the Master submachine CheckCompatibility_1
133 Figure 71 – Activity for state “CheckVxy”
Figure 72 – Activity for state “CheckCompV10”
134 Figure 73 – Activity for state “CheckComp”
Figure 74 – Activity (write parameter) in state “RestartDevice”
135 Figure 75 – SM Master submachine CheckSerNum_3
Table 85 – State transition tables of the Master submachine CheckSerNum_3
136 9.3 System management of the Device
9.3.1 Overview
Figure 76 – Activity (check SerialNumber) for state CheckSerNum_3
137 Figure 77 – Structure and services of the system management (Device)
138 9.3.2 SM Device services
Figure 78 – Sequence chart of the use case “INACTIVE – SIO – SDCI – SIO”
139 Table 86 – SM services within the Device
Table 87 – SM_SetDeviceCom
140 Table 88 – SM_GetDeviceCom
141 Table 89 – SM_SetDeviceIdent
142 Table 90 – SM_GetDeviceIdent
143 Table 91 – SM_SetDeviceMode
144 9.3.3 SM Device protocol
Table 92 – SM_DeviceMode
145 Figure 79 – State machine of the Device system management
Table 93 – State transition tables of the Device system management
148 Figure 80 – Sequence chart of a regular Device startup
149 Figure 81 – Sequence chart of a Device startup in compatibility mode
150 Figure 82 – Sequence chart of a Device startup when compatibility fails
151 10 Device
10.1 Overview
Figure 83 – Structure and services of a Device
152 10.2 Process Data Exchange (PDE)
10.3 Parameter Manager (PM)
10.3.1 General
10.3.2 Parameter manager state machine
153 Figure 84 – The Parameter Manager (PM) state machine
Table 94 – State transition tables of the PM state machine
154 10.3.3 Dynamic parameter
155 10.3.4 Single parameter
Figure 85 – Positive and negative parameter checking result
Table 95 – Definitions of parameter checks
156 10.3.5 Block parameter
Figure 86 – Positive block parameter download with Data Storage request
157 Figure 87 – Negative block parameter download
158 10.3.6 Concurrent parameterization access
10.3.7 Command handling
10.4 Data Storage (DS)
10.4.1 General
10.4.2 Data Storage state machine
159 Figure 88 – The Data Storage (DS) state machine
Table 96 – State transition table of the Data Storage state machine
160 10.4.3 DS configuration
10.4.4 DS memory space
Figure 89 – Data Storage request message sequence
161 10.4.5 DS Index_List
10.4.6 DS parameter availability
10.4.7 DS without ISDU
10.4.8 DS parameter change indication
10.5 Event Dispatcher (ED)
10.6 Device features
10.6.1 General
162 10.6.2 Device backward compatibility
10.6.3 Protocol revision compatibility
10.6.4 Factory settings
10.6.5 Application reset
10.6.6 Device reset
10.6.7 Visual SDCI indication
163 10.6.8 Parameter access locking
10.6.9 Data Storage locking
10.6.10 Device parameter locking
10.6.11 Device user interface locking
10.6.12 Offset time
Figure 90 – Cycle timing
164 10.6.13 Data Storage concept
10.6.14 Block Parameter
10.7 Device design rules and constraints
10.7.1 General
10.7.2 Process Data
10.7.3 Communication loss
10.7.4 Direct Parameter
165 10.7.5 ISDU communication channel
10.7.6 DeviceID rules related to Device variants
10.7.7 Protocol constants
Table 97 – Overview of the protocol constants for Devices
166 10.8 IO Device description (IODD)
10.9 Device diagnosis
10.9.1 Concepts
167 10.9.2 Events
Table 98 – Classification of Device diagnosis incidents
168 10.9.3 Visual indicators
Figure 91 – Event flow in case of successive errors
Figure 92 – Device LED indicator timing
Table 99 – Timing for LED indicators
169 10.10 Device connectivity
11 Master
11.1 Overview
11.1.1 Generic model for the system integration of a Master
11.1.2 Structure and services of a Master
Figure 93 – Generic relationship of SDCI technology and fieldbus technology
171 Figure 94 – Structure and services of a Master
Figure 95 – Relationship of the common Master applications
172 11.2 Configuration Manager (CM)
11.2.1 General
Table 100 – Internal variables and Events to control the common Master applications
173 Figure 96 – Sequence diagram of configuration manager actions
174 11.2.2 Configuration parameter
Figure 97 – Ports in MessageSync mode
176 11.2.3 State machine of the Configuration Manager
Figure 98 – State machine of the Configuration Manager
177 Table 101 – State transition tables of the Configuration Manager
178 11.3 Data Storage (DS)
11.3.1 Overview
11.3.2 DS data object
11.3.3 DS state machine
Figure 99 – Main state machine of the Data Storage mechanism
179 Figure 100 – Submachine “UpDownload_2” of the Data Storage mechanism
180 Figure 101 – Data Storage submachine “Upload_7”
Figure 102 – Data Storage upload sequence diagram
181 Figure 103 – Data Storage submachine “Download_10”
Figure 104 – Data Storage download sequence diagram
182 Table 102 – States and transitions of the Data Storage state machines
184 11.3.4 Parameter selection for Data Storage
11.4 On-Request Data exchange (ODE)
Figure 105 – State machine of the On-request Data Exchange
Table 103 – State transition table of the ODE state machine
185 11.5 Diagnosis Unit (DU)
186 11.6 PD Exchange (PDE)
11.6.1 General
11.6.2 Process Data mapping
Figure 106 – System overview of SDCI diagnosis information propagation via Events
187 11.6.3 Process Data invalid/valid qualifier status
Figure 107 – Process Data mapping from ports to the gateway data stream
Figure 108 – Propagation of PD qualifier status between Master and Device
188 11.7 Port and Device configuration tool (PDCT)
11.7.1 General
11.7.2 Basic layout examples
Figure 109 – Example 1 of a PDCT display layout
189 11.8 Gateway application
11.8.1 General
11.8.2 Changing Device configuration including Data Storage
11.8.3 Parameter server and recipe control
11.8.4 Anonymous parameters
Figure 110 – Example 2 of a PDCT display layout
190 11.8.5 Virtual port mode DIwithSDCI
Figure 111 – Alternative Device configuration
191 Figure 112 – Virtual port mode “DIwithSDCI”
Table 104 – State transitions of the state machine “DIwithSDCI”
193 Annex A (normative) Codings, timing constraints, and errors
Figure A.1 – M-sequence control
Table A.1 – Values of communication channel
194 Figure A.2 – Checksum/M-sequence type octet
Table A.2 – Values of R/W
Table A.3 – Values of M-sequence types
195 Figure A.3 – Checksum/status octet
Table A.4 – Data types for user data
Table A.5 – Values of PD status
196 Figure A.4 – Principle of the checksum calculation and compression
Table A.6 – Values of the Event flag
197 Figure A.5 – M-sequence TYPE_0
Figure A.6 – M-sequence TYPE_1_1
198 Figure A.7 – M-sequence TYPE_1_2
Figure A.8 – M-sequence TYPE_1_V
199 Figure A.9 – M-sequence TYPE_2_1
Figure A.10 – M-sequence TYPE_2_2
Figure A.11 – M-sequence TYPE_2_3
200 Figure A.12 – M-sequence TYPE_2_4
Figure A.13 – M-sequence TYPE_2_5
Figure A.14 – M-sequence TYPE_2_6
201 Figure A.15 – M-sequence TYPE_2_V
Table A.7 – M-sequence types for the STARTUP mode
Table A.8 – M-sequence types for the PREOPERATE mode
202 Table A.9 – M-sequence types for the OPERATE mode (legacy protocol)
Table A.10 – M-sequence types for the OPERATE mode
204 Figure A.16 – M-sequence timing
Table A.11 – Recommended MinCycleTimes
206 Figure A.17 – I-Service octet
Table A.12 – Definition of the nibble “I-Service”
207 Table A.13 – ISDU syntax
Table A.14 – Definition of nibble Length and octet ExtLength
208 Figure A.18 – Check of ISDU integrity via CHKPDU
Table A.15 – Use of Index formats
209 Figure A.19 – Examples of request formats for ISDUs
Figure A.20 – Examples of response ISDUs
210 Figure A.21 – Examples of read and write request ISDUs
211 Figure A.22 – Structure of StatusCode type 1
Figure A.23 – Structure of StatusCode type 2
Table A.16 – Mapping of EventCodes (type 1)
212 Figure A.24 – Indication of activated Events
Figure A.25 – Structure of the EventQualifier
Table A.17 – Values of INSTANCE
213 Table A.18 – Values of SOURCE
Table A.19 – Values of TYPE
Table A.20 – Values of MODE
214 Annex B (normative) Parameter and commands
Figure B.1 – Classification and mapping of Direct Parameters
215 Table B.1 – Direct Parameter page 1 and 2
216 Figure B.2 – MinCycleTime
Table B.2 – Types of MasterCommands
217 Figure B.3 – M-sequence Capability
Table B.3 – Possible values of MasterCycleTime and MinCycleTime
Table B.4 – Values of ISDU
218 Figure B.4 – RevisionID
Figure B.5 – ProcessDataIn
Table B.5 – Values of SIO
Table B.6 – Permitted combinations of BYTE and Length
220 Figure B.6 – Index space for ISDU data objects
Table B.7 – Implementation rules for parameters and commands
221 Table B.8 – Index assignment of data objects (Device parameter)
222 Table B.9 – Coding of SystemCommand (ISDU)
223 Table B.10 – Data Storage Index assignments
224 Table B.11 – Structure of Index_List
225 Table B.12 – Device locking possibilities
227 Table B.13 – Device status parameter
228 Table B.14 – Detailed Device Status (Index 0x0025)
229 Figure B.7 – Structure of the Offset Time
Table B.15 – Time base coding and values of Offset Time
231 Annex C (normative) ErrorTypes (ISDU errors)
Table C.1 – ErrorTypes
234 Table C.2 – Derived ErrorTypes
236 Annex D (normative) EventCodes (diagnosis information)
Table D.1 – EventCodes
238 Table D.2 – Basic SDCI EventCodes
239 Annex E (normative) Data types
Table E.1 – BooleanT
Table E.2 – BooleanT coding
240 Figure E.1 – Coding examples of UIntegerT
Table E.3 – UIntegerT
Table E.4 – IntegerT
241 Table E.5 – IntegerT coding (8 octets)
Table E.6 – IntegerT coding (4 octets)
Table E.7 – IntegerT coding (2 octets)
Table E.8 – IntegerT coding (1 octet)
242 Figure E.2 – Coding examples of IntegerT
Table E.9 – Float32T
Table E.10 – Coding of Float32T
243 Figure E.3 – Singular access of StringT
Table E.11 – StringT
Table E.12 – OctetStringT
244 Figure E.4 – Coding example of OctetStringT
Figure E.5 – Definition of TimeT
Table E.13 – TimeT
245 Table E.14 – Coding of TimeT
Table E.15 – TimeSpanT
Table E.16 – Coding of TimeSpanT
246 Figure E.6 – Example of an ArrayT data structure
Table E.17 – Structuring rules for ArrayT
Table E.18 – Example for the access of an ArrayT
247 Table E.19 – Structuring rules for RecordT
Table E.20 – Example 1 for the access of a RecordT
Table E.21 – Example 2 for the access of a RecordT
248 Figure E.7 – Example 2 of a RecordT structure
Figure E.8 – Example 3 of a RecordT structure
Table E.22 – Example 3 for the access of a RecordT
249 Figure E.9 – Write requests for example 3
250 Annex F (normative) Structure of the Data Storage data object
Table F.1 – Structure of the stored DS data object
Table F.2 – Associated header information for stored DS data objects
251 Annex G (normative) Master and Device conformity
Table G.1 – EMC test conditions for SDCI
252 Table G.2 – EMC test levels
253 Figure G.1 – Test setup for electrostatic discharge (Master)
Figure G.2 – Test setup for RF electromagnetic field (Master)
254 Figure G.3 – Test setup for fast transients (Master)
Figure G.4 – Test setup for RF common mode (Master)
255 Figure G.5 – Test setup for electrostatic discharges (Device)
Figure G.6 – Test setup for RF electromagnetic field (Device)
Figure G.7 – Test setup for fast transients (Device)
256 Figure G.8 – Test setup for RF common mode (Device)
257 Annex H (informative) Residual error probabilities
Figure H.1 – Residual error probability for the SDCI data integrity mechanism
259 Annex I (informative) Example sequence of an ISDU transmission
Figure I.1 – Example for ISDU transmissions (1 of 2)
261 Annex J (informative) Recommended methods for detecting parameter changes
Table J.1 – Proper CRC generator polynomials
262 Bibliography

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