ASTM-F419:1994 Edition

ASTM F419

Scope

1.1 This test method covers the measurement of carrier density in silicon epitaxial layers. The precision that can be expected depends upon the carrier-density inhomogeneities parallel and perpendicular to the junction and upon the carrier-density level.

1.2 The measurement requires the formation of Schottky or p-n junction diodes on or in the epitaxial layer. In this sense the method is destructive (see, however, 5.2).

1.3 Both n- and -type epitaxial layers can be evaluated, on substrates of the same or opposite types, if the layer thickness is greater than twice the zero-bias depletion width plus, for diffused diodes only, the junction depth (1). This test method is also applicable to bulk material.

1.4 This test method covers the carrier density range from about 4 X 10 13 to about 8 X 10 16 carriers/cm (resistivity range from about 0.1 to about 100 [omega][dot]cm in -type wafers and from about 0.24 to about 330 [omega][dot]cm in -type wafers).

1.5 This test method includes procedures for checking both capacitance- and voltage-measuring equipment.

1.6 This test method provides two means of calculating the carrier density from capacitance-voltage data: an incremental method (12.3.1) and a curve-fitting method (12.3.2).

Note 1-An alternative method for determining carrier density in epitaxial layers is given in Test Method F1392. This and a related method, DIN 50439, use a mercury-probe Schottky barrier contact rather than a fabricated p-n junction or Schottky diode. Therefore, measurements by Test Method F1392 and DIN 50439 may not be entirely comparable to those made by this test method. DIN 50439 is also applicable to gallium arsenide as well as to silicon.

1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in 11.8 and 11.14.

Keywords

Capacitance-voltage method; Carrier density (in semiconductors); Density-electronic applications; Dielectric breakdown/strength-semiconductor materials; Diodes; Epitaxial wafer; Gate bias; Inhomogeneities; Junction diode; Net carrier density (in semiconductors); Polished silicon wafers/slices; Resistance and resistivity; Schottky diode; Silicon semiconductors; Single-crystal silicon; Voltage; carrier density-silicon epitaxial layers, by capacitance-voltage; measurements on fabricated junction/Schottky diodes, test

ICS Code

ICS Number Code 31.080.10 (Diodes)

DOI: 10.1520/F0419-94