BS EN 60424-3:2016
$102.76
Ferrite cores. Guidelines on the limits of surface irregularities – ETD-cores, EER-cores, EC-cores and E-cores
| Published By | Publication Date | Number of Pages |
| BSI | 2016 | 22 |
This part of IEC 60424 gives guidelines on allowable limits of surface irregularities applicable to ETD-cores, EER-cores, EC-cores and E-cores in accordance with the relevant general specification.
This standard is a specification useful in the negotiations between ferrite core manufacturers and customers about surface irregularities.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 6 | English CONTENTS |
| 7 | FOREWORD |
| 9 | 1 Scope 2 Normative references 3 Terms and definitions |
| 10 | 4 Limits of surface irregularities 4.1 Chips and ragged edges 4.1.1 General 4.1.2 Chips and ragged edges on the mating surfaces 4.1.3 Chips and ragged edges on other surfaces Tables Table 1 – Allowable areas of chips for ETD-cores in mm2 |
| 11 | Table 2 – Allowable areas of chips for EER-cores in mm2 Table 3 – Allowable areas of chips for EC-cores in mm2 |
| 12 | Table 4 – Allowable areas of chips for E-cores in mm2 |
| 13 | Figures Figure 1 – Chip location for ETD-cores, EER-cores and EC-cores Figure 2 – Chip location for E-cores |
| 14 | Table 5 – Area and length reference for visual inspection |
| 15 | 4.2 Cracks 4.3 Flash 4.4 Pull-outs |
| 16 | Figure 3 – Cracks and pull-out location for ETD-cores, EER-cores and EC-cores |
| 17 | Figure 4 – Cracks and pull-out location for E-cores Table 6 – Limits for cracks |
| 18 | 4.5 Crystallites 4.6 Pores Figure 5 – Crystallites location for ETD-cores, EER-cores and EC-cores Figure 6 – Crystallites location for E-cores |
| 19 | Figure 7 – Pores location for ETD-cores, EER-cores and EC-cores Figure 8 – Pores location for E-cores |
