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BS EN 62271-101:2013+A1:2018

BS EN 62271-101:2013+A1:2018

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High-voltage switchgear and controlgear – Synthetic testing

Published By Publication Date Number of Pages
BSI 2018 258
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This part of IEC 62271 mainly applies to a.c. circuit-breakers within the scope of IEC 62271- 100. It provides the general rules for testing a.c. circuit-breakers, for making and breaking capacities over the range of test duties described in 6.102 to 6.111 of IEC 62271-100:2008, by synthetic methods.

It has been proven that synthetic testing is an economical and technically correct way to test high-voltage a.c. circuit-breakers according to the requirements of IEC 62271-100 and that it is equivalent to direct testing.

The methods and techniques described are those in general use. The purpose of this standard is to establish criteria for synthetic testing and for the proper evaluation of results. Such criteria will establish the validity of the test method without imposing restraints on innovation of test circuitry.

PDF Catalog

PDF Pages PDF Title
2 National foreword
96 CONTENTS
101 FOREWORD
103 1 Scope
2 Normative references
3 Terms and definitions
105 4 Synthetic testing techniques and methods for short-circuit breaking tests
4.1 Basic principles and general requirements for synthetic breaking test methods
4.1.1 General
106 4.1.2 High-current interval
4.1.3 Interaction interval
107 4.1.4 High-voltage interval
108 4.2 Synthetic test circuits and related specific requirements for breaking tests
4.2.1 Current injection methods
109 4.2.2 Voltage injection method
4.2.3 Duplicate circuit method (transformer or Skeats circuit)
110 4.2.4 Other synthetic test methods
4.3 Three-phase synthetic test methods
111 Table 1 – Test circuits for test duties T100s and T100a
Table 2 – Test parameters during three-phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,5
112 Table 3 – Test parameters during three-phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,3
Table 4 – Test parameters during three phase interruption for test-duties T10, T30, T60 and T100s, kpp = 1,2
113 5 Synthetic testing techniques and methods for short-circuit making tests
5.1 Basic principles and general requirements for synthetic making test methods
5.1.1 General
5.1.2 High-voltage interval
5.1.3 Pre-arcing interval
114 5.1.4 Latching interval and fully closed position
5.2 Synthetic test circuit and related specific requirements for making tests
5.2.1 General
5.2.2 Test circuit
5.2.3 Specific requirements
115 6 Specific requirements for synthetic tests for making and breaking performance related to the requirements of 6.102 through 6.111 of IEC 62271-100:2008
125 Table 5 – Synthetic test methods for test duties T10, T30, T60, T100s, T100a, SP, DEF, OP and SLF
127 Figures
Figure 1 – Interrupting process – Basic time intervals
Tables
128 Figure 2 – Examples of evaluation of recovery voltage
129 Figure 3 – Equivalent surge impedance of the voltage circuit for the current injection method
130 Figure 4 – Making process – Basic time intervals
131 Figure 5 – Typical synthetic making circuit for single-phase tests
132 Figure 6 – Typical synthetic making circuit for out-of-phase
133 Figure 7 – Typical synthetic make circuit for three-phase tests (kpp = 1,5)
134 Figure 8 – Comparison of arcing time settings during three-phase direct tests (left) and three-phase synthetic (right) for T100s with kpp = 1,5
135 Figure 9 – Comparison of arcing time settings during three-phase direct tests (left) and three-phase synthetic (right) for T100a with kpp = 1,5
136 Annex A (informative) Current distortion
143 Figure A.1 – Direct circuit, simplified diagram
Figure A.2 – Prospective short-circuit current
Figure A.3 – Distortion current
144 Figure A.4 – Distortion current
145 Figure A.5 – Simplified circuit diagram
146 Figure A.6 – Current and arc voltage characteristics for symmetrical current
147 Figure A.7 – Current and arc voltage characteristics for asymmetrical current
148 Figure A.8 – Reduction of amplitude and duration of final current loop of arcing
149 Figure A.9 – Reduction of amplitude and duration of final current loop of arcing
150 Figure A.10 – Reduction of amplitude and duration of final current loop of arcing
151 Figure A.11 – Reduction of amplitude and duration of final current loop of arcing
152 Annex B (informative) Current injection methods
153 Figure B.1 – Typical current injection circuit with voltage circuit in parallel with the test circuit-breaker
154 Figure B.2 – Injection timing for current injection scheme with circuit B.1
155 Figure B.3 – Examples of the determination of the interval of significant change of arc voltage from the oscillograms
156 Annex C (informative) Voltage injection methods
157 Figure C.1 – Typical voltage injection circuit diagram with voltage circuit in parallel with the auxiliary circuit-breaker (simplified diagram)
158 Figure C.2 – TRV waveshapes in a voltage injection circuit with the voltage circuit in parallel with the auxiliary circuit-breaker
159 Annex D (informative) Skeats or duplicate transformer circuit
160 Figure D.1 – Transformer or Skeats circuit
161 Figure D.2 – Triggered transformer or Skeats circuit
162 Annex E (normative) Information to be given and results to be recorded for synthetic tests
163 Annex F (normative) Synthetic test methods for circuit-breakerswith opening resistors
167 Figure F.1 – Test circuit to verify thermal re-ignition behaviour of the main interrupter
Figure F.2 – Test circuit to verify dielectric re-ignition behaviour of the main interrupter
168 Figure F.3 – Test circuit on the resistor interrupter
169 Figure F.4 – Example of test circuit for capacitive current switching tests on the main interrupter
Figure F.5 – Example of test circuit for capacitive current switching tests on the resistor interrupter
170 Annex G (informative) Synthetic methods for capacitive-current switching
173 Figure G.1 – Capacitive current circuits (parallel mode)
174 Figure G.2 – Current injection circuit
175 Figure G.3 – LC oscillating circuit
176 Figure G.4 – Inductive current circuit in parallel with LC oscillating circuit
177 Figure G.5 – Current injection circuit, normal recovery voltage applied to both terminals of the circuit-breaker
178 Figure G.6 – Synthetic test circuit (series circuit), normal recovery voltage applied to both sides of the test circuit breaker
179 Figure G.7 – Current injection circuit, recovery voltage applied to both sides of the circuit-breaker
180 Figure G.8 – Making test circuit
181 Figure G.9 – Inrush making current test circuit
182 Annex H (informative) Re-ignition methods to prolong arcing
183 Figure H.1 – Typical re-ignition circuit diagram for prolonging arc-duration
Figure H.2 – Combined Skeats and current injection circuits
184 Figure H.3 – Typical waveforms obtained during an asymmetrical test using the circuit in Figure H.2
185 Annex I (normative) Reduction in di/dt and TRV for test duty T100a
Table I.1 – Last loop di/dt reduction for 50 Hz for kpp = 1,3 and 1,5
186 Table I.2 – Last loop di/dt reduction for 50 Hz for kpp = 1,2
187 Table I.3 – Last loop di/dt reduction for 60 Hz for kpp = 1,3 and 1,5
188 Table I.4 – Last loop di/dt reduction for 60 Hz for kpp = 1,2
189 Table I.5 – Corrected TRV values for the first pole-to-clear for kpp = 1,3 and fr = 50 Hz
190 Table I.6 – Corrected TRV values for the first pole-to-clear for kpp = 1,3 and fr = 60 Hz
191 Table I.7 – Corrected TRV values for the first pole-to-clear for kpp = 1,5 and fr = 50 Hz
192 Table I.8 – Corrected TRV values for the first pole-to-clear for kpp = 1,5 and fr = 60 Hz
Table I.9 – Corrected TRV values for the first pole-to-clear for kpp = 1,2 and fr = 50 Hz
193 Table I.10 – Corrected TRV values for the first pole-to-clear for kpp = 1,2 and fr = 60 Hz
194 Annex J (informative) Three-phase synthetic test circuits
196 Figure J.1 – Three-phase synthetic combined circuit
197 Figure J.2 – Waveshapes of currents, phase-to-ground and phase-to phase voltages during a three-phase synthetic test (T100s; kpp = 1,5 ) performed according to the three-phase synthetic combined circuit
198 Figure J.3 – Three-phase synthetic circuit with injection in all phases for kpp = 1,5
Figure J.4 – Waveshapes of currents and phase-to-ground voltages during a three-phase synthetic test (T100s; kpp =1,5) performed according to the three-phase synthetic circuit with injection in all phases
199 Figure J.5 – Three-phase synthetic circuit for terminal fault tests with kpp = 1,3 (current injection method)
Figure J.6 – Waveshapes of currents, phase-to-ground and phase-to-phase voltages during a three-phase synthetic test (T100s; kpp =1,3 ) performed according to the three-phase synthetic circuit shown in Figure J.5
200 Figure J.7 – TRV voltages waveshapes of the test circuit described in Figure J.5
201 Annex K (normative) Test procedure using a three-phase current circuit and one voltage circuit
202 Table K.1 – Demonstration of arcing times for kpp = 1,5
203 Table K.2 – Alternative demonstration of arcing times for kpp = 1,5
204 Table K.3 – Demonstration of arcing times for kpp = 1,3
205 Table K.4 – Alternative demonstration of arcing times for kpp = 1,3
206 Table K.5 – Demonstration of arcing times for kpp = 1,5
207 Table K.6 – Alternative demonstration of arcing times for kpp = 1,5
208 Table K.7 – Demonstration of arcing times for kpp = 1,3
209 Table K.8 – Alternative demonstration of arcing times for kpp = 1,3
210 Table K.9 – Procedure for combining kpp = 1,5 and 1,3 during test-duties T10, T30, T60 and T100s(b)
211 Table K.10 – Procedure for combining kpp = 1,5 and 1,3 during test-duty T100a
212 Figure K.1 – Example of a three-phase current circuit with single-phase synthetic injection
213 Figure K.2 – Representation of the testing conditions of Table K.1
214 Figure K.3 – Representation of the testing conditions of Table K.2
215 Figure K.4 – Representation of the testing conditions of Table K.3
216 Figure K.5 – Representation of the testing conditions of Table K.4
217 Figure K.6 – Representation of the testing conditions of Table K.5
218 Figure K.7 – Representation of the testing conditions of Table K.6
219 Figure K.8 – Representation of the testing conditions of Table K.7
220 Figure K.9 – Representation of the testing conditions of Table K.8
221 Annex L (normative) Splitting of test duties in test series taking into account the associated TRV for each pole-to-clear
223 Table L.1 – Test procedure for kpp = 1,5
224 Table L.2 – Test procedure for kpp = 1,3
225 Table L.3 – Simplified test procedure for kpp = 1,3
226 Table L.4 – Test procedure for kpp = 1,2
227 Table L.5 – Simplified test procedure for kpp = 1,2
228 Table L.6 – Test procedure for asymmetrical currents in the case of kpp = 1,5
229 Table L.7 – Test procedure for asymmetrical currents in the case of kpp = 1,3
230 Table L.8 – Test procedure for asymmetrical currents in the case of kpp = 1,2
231 Figure L.1 – Graphical representation of the test shown in Table L.6
232 Figure L.2 – Graphical representation of the test shown in Table L.7
233 Table L.9 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,5 , fr = 50 Hz
234 Table L.10 – Required test parameters for different asymmetrical conditions in the case of a kpp = 1,3 , fr = 50 Hz
235 Table L.11 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,2 , fr = 50 Hz
236 Table L.12 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,5 , fr = 60 Hz
237 Table L.13 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,3 , fr = 60 Hz
238 Table L.14 – Required test parameters for different asymmetrical conditions in the case of kpp = 1,2, fr = 60 Hz
239 Table L.15 – Procedure for combining kpp = 1,5 and 1,3 during test-duties T10, T30, T60 and T100s(b)
240 Table L.16 – Procedure for combining kpp = 1,5 and 1,3 during test-duty T100a
241 Annex M (normative) Tolerances on test quantities for type tests
242 Table M.1 – Tolerances on test quantities for type tests (1 of 2)
244 Annex N (informative) Typical test circuits for metal-enclosed and dead tank circuit-breakers
245 Figure N.1 – Test circuit for unit testing (circuit-breaker with interaction due to gas circulation)
246 Figure N.2 – Half-pole testing of a circuit-breaker in test circuit given by Figure N.1 – Example of the required TRVs to be applied between the terminals of the unit(s) under test and between the live parts and the insulated enclosure
247 Figure N.3 – Synthetic test circuit for unit testing (if unit testing is allowed as per 6.102.4.2 of IEC 62271-100:2008)
248 Figure N.4 – Half-pole testing of a circuit-breaker in the test circuit of Figure N.3 – Example of the required TRVs to be applied between the terminals of the unit(s) under test and between the live parts and the insulated enclosure
249 Figure N.5 – Capacitive current injection circuit with enclosure of the circuit-breaker energized
250 Figure N.6 – Capacitive synthetic circuit using two power-frequency sources and with the enclosure of the circuit-breaker energized
251 Figure N.7 – Capacitive synthetic current injection circuit – Example of unit testing on half a pole of a circuit-breaker with two units per pole – Enclosure energized with d.c. voltage source
252 Figure N.8 – Symmetrical synthetic test circuit for out-of-phase switching tests on a complete pole of a circuit-breaker
253 Figure N.9 – Full pole test with voltage applied to both terminals and the metal enclosure
254 Annex O (informative) Combination of current injection and voltage injection methods
255 Figure O.1 – Example of combined current and voltage injection circuit with application of full test voltage to earth
256 Figure O.2 – Example of combined current and voltage injection circuit with separated application of test voltage
257 Bibliography

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BS EN 62271-101:2013+A1:2018
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