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BS EN IEC 62433-6:2020

BS EN IEC 62433-6:2020

$198.66

EMC IC modelling – Models of integrated circuits for Pulse immunity behavioural simulation. Conducted Pulse Immunity (ICIM-CPI)

Published By Publication Date Number of Pages
BSI 2020 60
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IEC 62433-6:2020 describes the extraction flow for deriving an immunity macro-model of an Integrated Circuit (IC) against conducted Electrostatic Discharge (ESD) according to IEC 61000-4-2 and Electrical Fast Transients (EFT) according to IEC 61000-4-4. The model addresses physical damages due to overvoltage, thermal damage and other failure modes. Functional failures can also be addressed. This model allows the immunity simulation of the IC in an application. This model is commonly called “Integrated Circuit Immunity Model Conducted Pulse Immunity”, ICIM-CPI. This document provides: – the description of ICIM-CPI macro-model elements representing electrical, thermal or logical behaviour of the IC. – a universal data exchange format based on XML.

PDF Catalog

PDF Pages PDF Title
2 undefined
5 Annex ZA(normative)Normative references to international publicationswith their corresponding European publications
6 English
CONTENTS
9 FOREWORD
11 1 Scope
2 Normative references
12 3 Terms, definitions, abbreviated terms and conventions
3.1 Terms and definitions
15 3.2 Abbreviated terms
3.3 Conventions
4 Philosophy
16 5 ICIM-CPI model structure
5.1 General
17 Figures
Figure 1 – Structure of the ICIM-CPI model
18 5.2 PPN
5.2.1 Typical structure of a PPN
Figure 2 – Example of an ICIM-CPI model of an electronic board
19 5.2.2 PDN description
Figure 3 – Structure of a typical PPN
20 5.2.3 NLB description
5.3 FB description
21 Figure 4 – Characteristics of a voltage pulse entering the DI during a TLP test
22 6 CPIML format
6.1 General
Figure 5 – Example of defect monitored at the OO when a disturbance is applied to the DI
23 6.2 CPIML structure
Figure 6 – CPIML inheritance hierarchy
24 6.3 Global elements
6.4 Header section
6.5 Lead_definitions section
Tables
Table 1 – Attributes of Lead tag in the Lead_definitions section
25 6.6 Macro-models section
Table 2 – Compatibility between the Mode and Type fields for correct CPIML annotation
26 6.7 Validity section
6.8 PDN
6.9 NLB
6.9.1 General
Table 3 – Definition of the Lead tag for Nlb section
27 6.9.2 Attribute definitions
28 6.9.3 Data description
Table 4 – Default values of Unit_voltage and Unit_current
Table 5 – Allowed file extensions for Data_files
29 6.10 FB
6.10.1 General
Figure 7 – Example of a NLB external file
30 6.10.2 Attribute definitions
Table 6 – Definition of the Lead tag in Fb section
31 Table 7 – Table sub-attributes definition
Table 8 – Pulse_characteristics parameters definition
32 Table 9 – Test_criteria parameters definition
34 6.10.3 Data description
37 Figure 8 – Example of an external FB file
38 Annex A (informative) Extraction of model components
A.1 General
A.2 PPN description
A.3 PDN Extraction
A.3.1 General
A.3.2 S/Z/Y-parameter measurement
39 A.3.3 Conventional one-port method
A.3.4 Two-port method for low impedance measurement
Figure A.1 – Conventional one-port S-parameters measurement
Figure A.2 – Two-port method for low impedance measurement
40 A.3.5 Two-port method for high impedance measurement
A.4 NLB extraction
A.4.1 General
Figure A.3 – Two-port method for high impedance measurement
41 A.4.2 TLP test method
Figure A.4 – Example of I/V measurements to extract NLB
42 Figure A.5 – TLP method set-up (not powered IC)
Figure A.6 – Example of NLB extraction using standard TLP pulse
43 A.5 FB extraction
A.5.1 General
A.5.2 Example of FB data in case of test criteria type = Class E_IC
44 Figure A.7 – Graphs for identification of IC failure mechanism for destruction prediction
45 A.5.3 Example of FB data in case of test criteria type = Class C_IC
Table A.1 – Example of FB data corresponding to Class EIC failure
Table A.2 – Example of FB data corresponding to Class CIC failure
46 Annex B (informative) NLB implementation techniques in a circuit simulator
B.1 General
B.2 NLB modelling based on a R/I table
B.3 NLB modelling based on a switch based model
Figure B.1 – NLB model based on a R/I table
47 B.4 NLB modelling based on physical device model
Figure B.2 – Example of a generic model architecture based on switches for NLB behavioural modelling
Figure B.3 – Example of core MOS large signal model of the GGNMOS
49 Annex C (informative) Example of ICIM-CPI model
C.1 General
C.2 Example of power switch ICIM-CPI model
C.2.1 General
C.2.2 CPImodel
Figure C.1 – Use of the ICIM-CPI model for simulation
50 Figure C.2 – Power switch V/I curve for 50 ns-pulse width
Figure C.3 – Power switch ICIM-CPI model
Table C.1 – Synthesis peak voltage and energy for different pulse widths
52 C.2.3 ICIM-CPI model use
53 Figure C.4 – Power switch ICIM-CPI model use for ESD protection design
Figure C.5 – Calculated voltage at power switch pin for different ESD protection capacitor values
54 C.3 Example of 32-bit microcontroller ICIM-CPI model
C.3.1 General
Figure C.6 – Voltage at power switch pin for fog lamp left and right sides
Figure C.7 – Example of 32-bit microcontroller protection devices
55 C.3.2 CPImodel
58 Bibliography

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