BSI PD IEC TR 62240-2:2018
$142.49
Process management for avionics. Electronic components capability in operation – Semiconductor microcircuit lifetime
| Published By | Publication Date | Number of Pages |
| BSI | 2018 | 32 |
This part of IEC 62240, which is a Technical Report, focuses on original equipment manufacturers (OEMs) using commercial off the shelf (COTS) semiconductor microcircuits for high performance, high reliability and long duration applications. This document supports OEMs in the preparation and maintenance of their semiconductor electronic component management plan (ECMP).
This document describes a process and a method for selecting digital semiconductor microcircuits by ensuring that their lifetime is compatible with the requirements of aerospace, defence and high performance (ADHP) applications (generally in connection with functional environments). Methods and guidelines are provided to assess the long term reliability of COTS semiconductor microcircuits in such applications; they mainly apply during the electronic design phase when selecting semiconductor microcircuits and assessing the application reliability.
Moreover, the document focuses on the intrinsic wear-out and the lifetime of COTS semiconductor microcircuits processed of less than or equal to 90 nm feature size (also called deep sub-micron (DSM) semiconductor microcircuits) and puts aside, at this time, packaging wear-out and random failure mechanisms. In this view, physics of failure (PoF) is at the heart of the approach.
NOTE 1 IEC 62239-1 can assist OEMs in the creation and maintenance of ECMPs.
NOTE 2 SAE ARP6338 can also help the OEM with regard to assessment and mitigation of early wear-out of life-limited semiconductor microcircuits.
NOTE 3 With the evolution of electronic technology and semiconductor microcircuits processed of less than or equal to 90 nm feature size, the current MIL-HDBK-217 handbook or FIDES guide become inappropriate as they are based for the time being on the assumption that the semiconductor electronic component exhibits a constant (random) failure rate and does not have life limits or exhibit wear-out.
Moreover, silicon itself has fundamentally very low failures in time (FIT) rates and the major failure modes are often in the packaging (for example housing, bond wires, etc.).
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | undefined |
| 4 | CONTENTS |
| 6 | FOREWORD |
| 8 | INTRODUCTION |
| 9 | 1 Scope 2 Normative references 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions |
| 12 | 3.2 Abbreviated terms |
| 13 | 4 Lifetime assessment process and method 4.1 General |
| 14 | Figure 1 – Process flow for lifetime assessment and selection ofCOTS semiconductor microcircuits |
| 15 | 4.2 Input data for the method 4.2.1 General 4.2.2 COTS semiconductor microcircuits and lifetime issues considerations 4.2.3 Operating and thermal conditions 4.3 Lifetime requirements in mission 4.3.1 Lifetime requirements for electronic equipment in mission |
| 16 | 4.3.2 Lifetime requirement for COTS semiconductor microcircuit 4.4 Lifetime assessment for COTS semiconductor microcircuit based on the OCM information 4.4.1 Availability of lifetime assessment by the OCM 4.4.2 Lifetime compliance 4.5 Lifetime assessment for a COTS semiconductor microcircuit processed by the OEM 4.5.1 Approach |
| 17 | 4.5.2 Risk analysis based on physics of failure (PoF) and the component family 4.5.3 OCM’s technical data availability and relevance 4.5.4 Acceleration models assessment paths |
| 18 | 4.6 Lifetime calculation of COTS semiconductor microcircuit in mission 4.7 Lifetime compliance of COTS semiconductor microcircuit in mission |
| 19 | 4.8 Situation reconsideration and alternatives 4.8.1 General 4.8.2 Semiconductor microcircuits change 4.8.3 Lifetime mitigation solutions |
| 20 | 4.9 Final report |
| 21 | 5 Considerations with regard to semiconductor ageing level estimation for semiconductor microcircuits |
| 22 | Annex A (informative)Failure and degradation mechanisms ofCOTS semiconductor microcircuits Tables Table A.1 – Some failure and degradation mechanisms forCOTS semiconductor microcircuits |
| 24 | Annex B (informative)Example of operating and thermal mission profile for a COTS semiconductor microcircuit Figure B.1 – Example of thermal and operating mission profile for a semiconductormicrocircuit implemented in an electronic equipment located on the avionic bayof a civil aircraft, assuming 30 °C of thermal dissipation |
| 25 | Annex C (informative)Risk of failure and degradation mechanisms accordingto the type of COTS semiconductor microcircuit Table C.1 – Typical failure and degradation mechanisms according to theCOTS semiconductor microcircuit family and structure |
| 26 | Annex D (informative)BEOL and FEOL technological parameters Table D.1 – BEOL and FEOL technological parameters |
| 27 | Annex E (informative)Generic acceleration models Table E.1 – Examples of generic acceleration model basedon the failure and degradation mechanism, and basedon the internal semiconductor microcircuit structure |
| 28 | Annex F (informative)Final report Table F.1 – Template for final report |
| 30 | Bibliography |
Related products
-
BSI PD IEC TR 62240-2:2018
Process management for avionics. Electronic components capability in operation – Semiconductor microcircuit lifetime Published By…
