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BSI PD IEC/TR 63133:2017:2018 Edition

BSI PD IEC/TR 63133:2017:2018 Edition

$102.76

Semiconductor devices. Scan based ageing level estimation for semiconductor devices

Published By Publication Date Number of Pages
BSI 2018 20
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This Technical Report specifies a design technique of performance estimation storage element, which can monitor semiconductor ageing and characterize ageing level. The estimated ageing level can be used to improve the reliability of system.

PDF Catalog

PDF Pages PDF Title
2 undefined
4 CONTENTS
5 FOREWORD
7 INTRODUCTION
Figures
Figure 1 – Reliability bathtub curve
8 1 Scope
2 Normative references
3 Terms, definitions and abbreviated terms
3.1 Terms and definitions
9 3.2 Abbreviations
11 4 Ageing level
4.1 Overview
4.2 Ageing level characterization technique (test method)
Figure 2 – Schematic of ageing level estimation technique
12 Figure 3 – A guard band and estimated ageing level
13 4.3 Architecture and operation
Figure 4 – Ageing level monitoring and scan chain architecture
14 4.4 Performance estimation storage element
Figure 5 – State diagram for performance estimation controller
15 Figure 6 – Modified scan cell architecture
Figure 7 – Operations of shadow latch, storage element, and PERCaccording to CLK and PECLK
16 4.5 Simulation results
4.6 Experimental results
Figure 8 – Simulation results for a case in which ageing occurs on a data path
17 Table 1 – Power consumption compared with prior work
18 Figure 9 – PECLKs for various delay points and their results
19 Bibliography

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BSI PD IEC/TR 63133:2017
$102.76