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IEEE 1076.6-2004

$184.17

IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis

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IEEE 2004
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Revision Standard – Inactive-Withdrawn. This document specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

PDF Catalog

PDF Pages PDF Title
1 IEEE Std 1076.6-2004 Cover Page
2 Title Page
4 Introduction
5 Development of IEEE Std 1076.6-1999
6 Notice to users
Participants
7 CONTENTS
8 1. Overview
1.1 Scope
1.2 Compliance to this standard
9 1.3 Terminology
1.4 Conventions
10 2. References
3. Definitions and acronyms
3.1 Definitions
11 3.2 Acronyms
12 4. Predefined types
5. Verification methodology
13 5.1 Combinational verification
5.2 Sequential verification
14 6. Modeling hardware elements
6.1 Edge-sensitive sequential logic
26 6.2 Level-sensitive sequential logic
30 6.3 Three-state logic and busses
6.4 Combinational logic
31 6.5 ROM and RAM memories
36 7. Pragmas
7.1 Attributes
53 7.2 Metacomments
54 8. Syntax
8.1 Design entities and configurations
59 8.2 Subprograms and packages
63 8.3 Types
68 8.4 Declarations
74 8.5 Specifications
76 8.6 Names
78 8.7 Expressions
82 8.8 Sequential statements
88 8.9 Concurrent statements
93 8.10 Scope and visibility
94 8.11 Design units and their analysis
95 8.12 Elaboration
8.13 Lexical elements
8.14 Predefined language environment
98 Annex A
Annex A (informative) Syntax summary
117 Annex B
Annex B (normative) Synthesis package RTL_ATTRIBUTES
118 Index
A-M
119 I
K
L
M
O
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0-Z
IEEE 1076.6-2004
$184.17