{"id":416353,"date":"2024-10-20T06:10:17","date_gmt":"2024-10-20T06:10:17","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-iec-62680-4-12022\/"},"modified":"2024-10-26T11:27:52","modified_gmt":"2024-10-26T11:27:52","slug":"bs-en-iec-62680-4-12022","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-iec-62680-4-12022\/","title":{"rendered":"BS EN IEC 62680-4-1:2022"},"content":{"rendered":"

The specification is primarily targeted at peripheral developers and platform\/adapter developers, but provides valuable information for platform operating system\/BIOS\/device driver, adapter independent hardware vendors\/independent software vendors, and system OEMs. This specification can be used for developing new products and associated software.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
2<\/td>\nundefined <\/td>\n<\/tr>\n
4<\/td>\nEuropean foreword
Endorsement notice <\/td>\n<\/tr>\n
5<\/td>\nFOREWORD <\/td>\n<\/tr>\n
18<\/td>\nCONTENTS <\/td>\n<\/tr>\n
44<\/td>\n1 Introduction
1.1 Scope of the Document
1.2 USB Product Compliance
1.3 Document Organization
1.4 Design Goals
1.5 Related Documents <\/td>\n<\/tr>\n
45<\/td>\n1.6 Conventions
1.6.1 Precedence
1.6.2 Keywords <\/td>\n<\/tr>\n
46<\/td>\n1.6.3 Capitalization
1.6.4 Italic Text
1.6.5 Numbering
1.6.6 Bit, Byte, DW, and Symbol Conventions
1.6.7 Implementation Notes
1.6.8 Connection Manager Notes
1.6.9 Pseudocode <\/td>\n<\/tr>\n
47<\/td>\n1.6.10 CRC Algorithms
1.6.11 FourCC
1.7 Reserved Values and Fields
Tables
Table 11. Rsvd Value and Field Handling <\/td>\n<\/tr>\n
48<\/td>\n1.8 Terms and Abbreviations <\/td>\n<\/tr>\n
53<\/td>\n2 Architectural Overview
2.1 USB4 System Description <\/td>\n<\/tr>\n
54<\/td>\nFigures
Figure 21. USB4\/USB3.2 Dual Bus System Architecture <\/td>\n<\/tr>\n
55<\/td>\n2.1.1 Architectural Constructs <\/td>\n<\/tr>\n
56<\/td>\nFigure 22. Single-Lane USB4 Link
Figure 23. Dual-Lane USB4 Link <\/td>\n<\/tr>\n
57<\/td>\nFigure 24. Example of a USB4-Based Dock <\/td>\n<\/tr>\n
58<\/td>\n2.1.2 USB4 Mechanical
2.1.3 USB4 Power
2.1.4 USB4 System Configuration
2.1.5 Thunderbolt\u2122 3 (TBT3) Compatibility Support <\/td>\n<\/tr>\n
59<\/td>\n2.1.6 USB Type-C Alternate Mode Compatibility Support
2.2 USB4 Fabric Architecture
2.2.1 USB4 Functional Stack
Figure 25. USB4 Functional Stack Layers <\/td>\n<\/tr>\n
60<\/td>\nFigure 26. USB4 Port (Lane Adapter), Protocol Adapter and Control Adapter across Functional Layers <\/td>\n<\/tr>\n
61<\/td>\n2.2.2 USB4 Fabric Topology
Figure 27. Example USB4 Physical Topology (No Loop) and Spanning Tree <\/td>\n<\/tr>\n
62<\/td>\n2.2.3 Paths
Figure 28. Example USB4 Physical Topology (with Loop) and Spanning Tree <\/td>\n<\/tr>\n
63<\/td>\nFigure 29. Paths across a USB4 Fabric <\/td>\n<\/tr>\n
64<\/td>\n2.2.4 Communication Constructs
Figure 210. USB4 Communication by Functional Layer <\/td>\n<\/tr>\n
65<\/td>\nFigure 211. Example Control Packet Traversing Several Routers <\/td>\n<\/tr>\n
66<\/td>\n2.2.5 USB4 Host-to-Host Communications
2.2.6 Programming Model
Figure 212. Example USB4 Host-to-Host Connections <\/td>\n<\/tr>\n
67<\/td>\n2.2.7 Time Synchronization
2.2.8 USB4 Fabric Data Integrity <\/td>\n<\/tr>\n
68<\/td>\n2.2.9 Global Life of a Router
2.2.10 Protocol Tunneling <\/td>\n<\/tr>\n
69<\/td>\nFigure 213 Example of a USB4 Host with USB3 Tunneling Highlighted <\/td>\n<\/tr>\n
70<\/td>\nFigure 214. Example of a USB4 Hub with USB3 Tunneling Highlighted
Figure 215. Example of a USB4 Peripheral Device with USB3 Tunneling Highlighted <\/td>\n<\/tr>\n
71<\/td>\nFigure 216. Protocol Stack for USB3 Tunneling <\/td>\n<\/tr>\n
72<\/td>\nFigure 217. Example of a USB4 Fabric with USB3 Tunneling <\/td>\n<\/tr>\n
73<\/td>\nFigure 218. Protocol Stacks along a USB3 Tunnel
Figure 219. Example Topology for DisplayPort Tunneling <\/td>\n<\/tr>\n
74<\/td>\nFigure 220. DP IN and OUT Protocol Adapters in LTTPR Non-Transparent and LTTPR Transparent Modes <\/td>\n<\/tr>\n
75<\/td>\nFigure 221. DP IN and OUT Protocol Adapters in Non-LTTPR Mode <\/td>\n<\/tr>\n
76<\/td>\nFigure 222. Protocol Stacks along a DisplayPort Tunneled Path <\/td>\n<\/tr>\n
77<\/td>\nFigure 223. Example Structure of a USB4 Host with PCIe Tunneling Highlighted
Figure 224. Example USB4 Hub with PCIe Tunneling Highlighted <\/td>\n<\/tr>\n
78<\/td>\nFigure 225. Example USB4 Device with PCIe Tunneling Highlighted
Figure 226. Protocol Stack for PCIe Tunneling <\/td>\n<\/tr>\n
79<\/td>\nFigure 227. Example of a USB4 Fabric with PCIe Tunneling <\/td>\n<\/tr>\n
80<\/td>\nFigure 228. Protocol Stacks along a PCIe Tunnel <\/td>\n<\/tr>\n
81<\/td>\nFigure 229. Protocol Stacks along a Path between Hosts <\/td>\n<\/tr>\n
82<\/td>\n3 Electrical Layer
Figure 230. Descriptor Ring and Data Buffers <\/td>\n<\/tr>\n
83<\/td>\n3.1 Sideband Channel Electrical Specifications <\/td>\n<\/tr>\n
84<\/td>\n3.2 USB4 Ecosystem
3.2.1 Insertion-Loss Considerations (Informative)
Table 31. SBTX and SBRX Specifications <\/td>\n<\/tr>\n
85<\/td>\n3.2.2 Coded Bit-Error-Ratio Considerations (Informative)
3.3 USB4 Electrical Compliance Methodology
3.3.1 System Compliance Test Point Definitions
Figure 31. Combined Forward-Error-Correction and Pre-Coding Scheme <\/td>\n<\/tr>\n
86<\/td>\n3.3.2 AC Coupling Capacitors
Figure 32. Compliance Points Definition
Figure 33. Examples for AC-Coupling Capacitor Placement
Table 32. Electrical Compliance Test Points <\/td>\n<\/tr>\n
87<\/td>\n3.3.3 Reference Clock-and-Data-Recovery (CDR) Function
3.3.4 Reference Equalization Function
Figure 34. Jitter Transfer Function <\/td>\n<\/tr>\n
88<\/td>\nFigure 35. Reference Receiver Equalization <\/td>\n<\/tr>\n
89<\/td>\nFigure 36. Frequency Response of Gen 2 Reference CTLE
Figure 37. Frequency Response of Gen 3 Reference CTLE <\/td>\n<\/tr>\n
90<\/td>\n3.3.5 Time Domain Measurements
3.3.6 Compliance Boards
3.4 Router Assembly Transmitter Compliance
3.4.1 Transmitter Specifications Applied for All Speeds <\/td>\n<\/tr>\n
91<\/td>\nTable 33. Transmitter Specifications Applied for All Speeds (at TP2) <\/td>\n<\/tr>\n
92<\/td>\nTable 34. Transmitter Frequency Variation Limits During Link Training Before Obtaining Steady-State <\/td>\n<\/tr>\n
93<\/td>\n Figure 38. Router Assembly Transmitter Frequency Variation During Training
Figure 39. Example Transmitter Frequency During Steady-State <\/td>\n<\/tr>\n
94<\/td>\nFigure 310. TX Differential Return Loss Mask <\/td>\n<\/tr>\n
95<\/td>\nFigure 311. TX Common-Mode Return Loss Mask <\/td>\n<\/tr>\n
96<\/td>\nFigure 312. Transmitter Equalizer Structure
Table 35. Transmit Equalization Presets <\/td>\n<\/tr>\n
97<\/td>\nFigure 313. Transmitter Equalization Frequency Response for Gen 2 Systems <\/td>\n<\/tr>\n
98<\/td>\n3.4.2 Transmitter Compliance Specifications for Gen 2
Table 36. Gen 2 Transmitter Specifications at TP2 <\/td>\n<\/tr>\n
99<\/td>\nTable 37. Gen 2 Transmitter Specifications at TP3 <\/td>\n<\/tr>\n
100<\/td>\n3.4.3 Transmitter Compliance Specifications for Gen 3 Interconnects
Figure 315. TX Mask Notations
Table 38. Gen 3 Transmitter Specifications at TP2 <\/td>\n<\/tr>\n
101<\/td>\n3.5 Router Assembly Receiver Compliance
3.5.1 Receiver Specifications Applied for All Speeds
Table 39. Gen 3 Transmitter Specifications at TP3
Table 310. Common Receiver Specifications at TP3\u2019 <\/td>\n<\/tr>\n
103<\/td>\nFigure 316. RX Differential Return-Loss Mask <\/td>\n<\/tr>\n
104<\/td>\n3.5.2 Receiver Uncoded BER Tolerance Testing
Figure 317. RX Common Mode Return-Loss Mask <\/td>\n<\/tr>\n
105<\/td>\nFigure 318. Receiver Tolerance Test Topologies
Figure 319. Receiver Tolerance Test Setups <\/td>\n<\/tr>\n
106<\/td>\n3.5.3 Receiver Multi Error-Bursts Testing
Table 311. Stressed Signal for Gen 2 Receiver Compliance Testing
Table 312. Stressed Signal for Gen 3 Receiver Compliance Testing <\/td>\n<\/tr>\n
108<\/td>\n3.6 Captive Device Compliance
3.6.1 Captive Device Compliance Test Setup
3.6.2 Captive Device Transmitter Specifications
Figure 320. Captive Device Compliance Test Setup
Table 313. Wireless Band Conducted Limits (at TP3) <\/td>\n<\/tr>\n
109<\/td>\nTable 314. Captive Device Transmitter Specifications at TP3 Applied for All Speeds <\/td>\n<\/tr>\n
110<\/td>\nTable 315. Captive Device Transmitter Specifications at TP3 for Gen 2 Systems <\/td>\n<\/tr>\n
111<\/td>\nTable 316. Captive Device Transmitter Specifications at TP3 for Gen 3 Systems <\/td>\n<\/tr>\n
112<\/td>\n3.6.3 Captive Device Receiver Specifications
Table 317. Common Receiver Specifications at TP2 <\/td>\n<\/tr>\n
114<\/td>\n3.6.4 Captive Device Receiver Uncoded BER Tolerance Testing
Table 318. Stressed Receiver Conditions for Gen 2 Captive Device Compliance Testing (at TP2)
Table 319. Stressed Receiver Conditions for Gen 3 Captive Device Compliance Testing (at TP2) <\/td>\n<\/tr>\n
115<\/td>\n3.6.5 Captive Device Receiver Multi Error-Bursts Testing
Figure 321. Captive Device Receiver Test Setup <\/td>\n<\/tr>\n
116<\/td>\n3.7 Low Frequency Periodic Signaling (LFPS)
3.7.1 LFPS Signal Definition
Table 320. LFPS Electrical Specifications <\/td>\n<\/tr>\n
117<\/td>\n3.8 Receiver Lane Margining (Testability)
3.8.1 Background
Figure 322. Signaling During Power Management State Exit <\/td>\n<\/tr>\n
118<\/td>\nFigure 323. Software Margining Mode Example <\/td>\n<\/tr>\n
119<\/td>\n3.8.2 Receiver Voltage Margining and Timing Margining Requirements
Figure 324. Hardware Margining Flow
Table 321. RX Margining Voltage and Timing Requirements <\/td>\n<\/tr>\n
120<\/td>\nFigure 325. RX Margining Range Requirements <\/td>\n<\/tr>\n
121<\/td>\n3.8.3 Receiver Parameter Access
Figure 326. Optional RX Margining Range Capabilities
Table 322. Optional RX Margining Voltage Capabilities <\/td>\n<\/tr>\n
122<\/td>\n4 Logical Layer
4.1 Sideband Channel <\/td>\n<\/tr>\n
123<\/td>\n4.1.1 Transactions
Figure 41. Cable Topologies (Informative) <\/td>\n<\/tr>\n
124<\/td>\nFigure 42. Symbol and Bit Order on Sideband Channel
Table 41. LT Transaction Format
Table 42. LSE Symbol <\/td>\n<\/tr>\n
125<\/td>\nTable 43. AT Transaction Format
Table 44. STX Symbol for an AT Transaction <\/td>\n<\/tr>\n
126<\/td>\nTable 45. Broadcast RT Transaction Format
Table 46. STX Symbol for a Broadcast RT Transaction
Table 47. Contents of Byte 2 in a Broadcast RT Transaction <\/td>\n<\/tr>\n
127<\/td>\nFigure 43. Propagation of a Broadcast RT Transaction
Table 48. Contents of Byte 3 in a Broadcast RT Transaction
Table 49. Addressed RT Transaction Format <\/td>\n<\/tr>\n
128<\/td>\nTable 410. STX Symbol for an Addressed RT Transaction <\/td>\n<\/tr>\n
130<\/td>\nFigure 44. Sideband Channel Receive Transaction State Machine <\/td>\n<\/tr>\n
131<\/td>\nTable 411. Sideband Channel Receive Transaction State Machine <\/td>\n<\/tr>\n
132<\/td>\nTable 412. AT\/RT Command Data Symbols
Table 413. AT\/RT Response Data Symbols
Table 414. Processing of a Received AT\/RT Command <\/td>\n<\/tr>\n
135<\/td>\nTable 415. SB Registers
Table 416. SB Register Fields Access Types
Table 417. SB Register Fields <\/td>\n<\/tr>\n
139<\/td>\n4.1.2 Lane Initialization <\/td>\n<\/tr>\n
140<\/td>\nFigure 45. Overview of Lane Initialization <\/td>\n<\/tr>\n
141<\/td>\nFigure 46. Example of Lane Reversal <\/td>\n<\/tr>\n
142<\/td>\nTable 418. Lane Attributes <\/td>\n<\/tr>\n
144<\/td>\nFigure 47. Progression of Link Equalization <\/td>\n<\/tr>\n
146<\/td>\n4.2 Logical Layer State Machine
4.2.1 Lane Adapter State Machine
Figure 48. The Lane Adapter State Machine <\/td>\n<\/tr>\n
148<\/td>\nFigure 49. Training Sub-State Machine <\/td>\n<\/tr>\n
149<\/td>\nTable 419. Transmitter Behavior in Training Sub-states
Table 420. Training Sub-State Machine Transitions <\/td>\n<\/tr>\n
151<\/td>\nTable 421. SLOS1 (64b\/66b Encoding) <\/td>\n<\/tr>\n
152<\/td>\nTable 422. SLOS2 (64b\/66b Encoding) <\/td>\n<\/tr>\n
153<\/td>\nTable 423. SLOS1 (128b\/132b Encoding) <\/td>\n<\/tr>\n
154<\/td>\nTable 424. SLOS2 (128b\/132b Encoding)
Table 425. TS1 and TS2 Ordered Sets <\/td>\n<\/tr>\n
156<\/td>\nFigure 410. Lane Bonding Sub-State Machine
Table 426. Transmitter Behavior in Bonding Sub-States
Table 427. Lane Bonding Sub-State Machine Transitions <\/td>\n<\/tr>\n
157<\/td>\nTable 428. CL2_REQ Ordered Set <\/td>\n<\/tr>\n
158<\/td>\nTable 429. CL1_REQ Ordered Set
Table 430. CL2_ACK Ordered Set
Table 431. CL1_ACK Ordered Set
Table 432. CL0s_ACK Ordered Set
Table 433. CL_NACK Ordered Set <\/td>\n<\/tr>\n
159<\/td>\nTable 434. CL_OFF Ordered Set <\/td>\n<\/tr>\n
160<\/td>\nFigure 411. Structure of a CL_WAKE1.X Ordered Set Symbol <\/td>\n<\/tr>\n
173<\/td>\n4.2.2 USB4 Link Transitions <\/td>\n<\/tr>\n
176<\/td>\n4.2.3 Logical Layer Link State
4.3 USB4 Link Encoding <\/td>\n<\/tr>\n
177<\/td>\nFigure 412. Packet Flow in the Logical Layer <\/td>\n<\/tr>\n
178<\/td>\n4.3.1 Lane Distribution
Figure 413. Byte Transmission Order on Lanes <\/td>\n<\/tr>\n
179<\/td>\n4.3.2 Symbol Encoding
Figure 414. Byte Ordering of Transport Layer Packets to the Logical Layer
Figure 415. Byte Ordering of Idle Packets to the Logical Layer <\/td>\n<\/tr>\n
180<\/td>\n4.3.3 Ordered Sets
Figure 416. Symbol Encoding of Data Symbols
Table 435. Ordered Set Structure <\/td>\n<\/tr>\n
181<\/td>\n4.3.4 Bit Swap
Figure 417. Symbol Encoding of Ordered Set Symbols <\/td>\n<\/tr>\n
182<\/td>\nFigure 418. Bit and Byte Ordering on the Wire \u2013 Data Symbol Payload <\/td>\n<\/tr>\n
183<\/td>\n4.3.5 Scrambling
Figure 419. Bit and Byte Ordering on the Wire \u2013 Ordered Set Symbol Payload
Table 436. Scrambling Rules <\/td>\n<\/tr>\n
184<\/td>\n4.3.6 RS-FEC <\/td>\n<\/tr>\n
186<\/td>\nFigure 420. RS-FEC Data Structures <\/td>\n<\/tr>\n
187<\/td>\n4.4 USB4 Link Operation
4.4.1 Start of Data
4.4.2 Error Cases and Recovery
Table 437. START_RS_FEC Bit Sequence <\/td>\n<\/tr>\n
188<\/td>\nTable 438. Error Cases and Impact on Logical Layer <\/td>\n<\/tr>\n
189<\/td>\n4.4.3 Clock Compensation and SKIP
4.4.4 Dual-Lane Skew
Table 439. SKIP Ordered Set <\/td>\n<\/tr>\n
190<\/td>\n4.4.5 Disconnect
Table 440. De-Skew Ordered Set <\/td>\n<\/tr>\n
193<\/td>\n4.4.6 Lane Adapter Disable and Enable <\/td>\n<\/tr>\n
195<\/td>\nFigure 421. Lane Disable of the Upstream Adapter <\/td>\n<\/tr>\n
196<\/td>\nFigure 422. Lane Disable Flow <\/td>\n<\/tr>\n
197<\/td>\n4.4.7 Time Sync Notification Ordered Set (TSNOS)
4.5 Sleep and Wake
4.5.1 Entry to Sleep
Table 441. TSN Ordered Set <\/td>\n<\/tr>\n
199<\/td>\n4.5.2 Behavior in Sleep State
4.5.3 Wake Events
Table 442. Router State Retained During Sleep <\/td>\n<\/tr>\n
200<\/td>\n4.5.4 Exit from Sleep
Table 443. Wake Events <\/td>\n<\/tr>\n
201<\/td>\n4.6 Timing Parameters
Table 444. Logical Layer Timing Parameters <\/td>\n<\/tr>\n
204<\/td>\n5 Transport Layer
5.1 Transport Layer Packets
5.1.1 Bit\/Byte Conventions <\/td>\n<\/tr>\n
205<\/td>\n5.1.2 Format
Figure 51. Convention for Transport Layer Diagrams
Figure 52. Transport Layer Packet Format
Table 51. Transport Layer Packet Header Format <\/td>\n<\/tr>\n
207<\/td>\n5.1.3 Transport Layer Packets <\/td>\n<\/tr>\n
208<\/td>\nFigure 53. Idle Packet Contents
Table 52. Credit Grant Packet Header
Table 53. Credit Grant Record Format <\/td>\n<\/tr>\n
209<\/td>\nFigure 54. Credit Grant Packet Format
Figure 55. Path Credit Sync Packet Format
Table 54. Path Credit Sync Packet Header
Table 55. Path Credit Sync Packet Payload <\/td>\n<\/tr>\n
210<\/td>\n5.1.4 Effect of Link State on Transport Layer Packets
Figure 56. Shared Buffers Credit Sync Packet Format
Table 56. Shared Buffers Credit Sync Packet Header
Table 57. Shared Buffers Credit Sync Packet Payload
Table 58. Transport Layer Behavior per Link State <\/td>\n<\/tr>\n
211<\/td>\n5.1.5 Minimum Headers Gap
Table 59. Minimum Transport Layer Header Gap Requirements <\/td>\n<\/tr>\n
212<\/td>\n5.2 Routing
5.2.1 Adapter Numbering Rules
Figure 57. Two Concurrent Data Symbols Example <\/td>\n<\/tr>\n
213<\/td>\n5.2.2 HopID Rules <\/td>\n<\/tr>\n
214<\/td>\n5.2.3 Routing Tables <\/td>\n<\/tr>\n
215<\/td>\n5.2.4 Routing Rules
Figure 58. Routing Table <\/td>\n<\/tr>\n
217<\/td>\n5.2.5 Connectivity Rules
Figure 59. Routing Example <\/td>\n<\/tr>\n
218<\/td>\n5.3 Quality of Service (QOS)
5.3.1 Packet Ordering
5.3.2 Flow Control
Figure 510. Example of Connectivity for USB3 Adapters <\/td>\n<\/tr>\n
219<\/td>\nTable 510. Ingress Adapter Flow Control Schemes <\/td>\n<\/tr>\n
220<\/td>\nTable 511. Buffer Allocation Parameters <\/td>\n<\/tr>\n
224<\/td>\nTable 512. Egress Adapter Flow Control Schemes <\/td>\n<\/tr>\n
226<\/td>\n5.3.3 Bandwidth Arbitration and Priority <\/td>\n<\/tr>\n
227<\/td>\nFigure 511. Egress Adapter Scheduler <\/td>\n<\/tr>\n
228<\/td>\n5.3.4 Packet Forwarding Delay Jitter
5.4 Path Tear-down
5.4.1 Egress Adapter <\/td>\n<\/tr>\n
229<\/td>\n5.4.2 Ingress Adapter
5.5 Timing Parameters
Table 513. Transport Layer Timing Parameters <\/td>\n<\/tr>\n
230<\/td>\n6 Configuration Layer
6.1 Domain Topology
6.2 Router Addressing <\/td>\n<\/tr>\n
231<\/td>\nFigure 61. Example of TopologyID Assignment <\/td>\n<\/tr>\n
232<\/td>\n6.3 Router States
Figure 62. Host Router State Machine <\/td>\n<\/tr>\n
233<\/td>\n6.3.1 Uninitialized Unplugged State
6.3.2 Uninitialized Plugged State
6.3.3 Sleep State
6.3.4 Enumerated State <\/td>\n<\/tr>\n
234<\/td>\n6.4 Control Packet Protocol
6.4.1 Control Adapter
6.4.2 Control Packets
Table 61. Control Packet Payload <\/td>\n<\/tr>\n
235<\/td>\nTable 62. Content of a Read Request <\/td>\n<\/tr>\n
237<\/td>\nTable 63. Content of a Read Response <\/td>\n<\/tr>\n
238<\/td>\nTable 64. Content of a Write Request <\/td>\n<\/tr>\n
240<\/td>\nTable 65. Content of a Write Response <\/td>\n<\/tr>\n
241<\/td>\nTable 66. Content of a Notification Packet <\/td>\n<\/tr>\n
242<\/td>\nTable 67. Content of a Notification Acknowledgement Packet
Table 68. Content of a Hot Plug Event Packet <\/td>\n<\/tr>\n
243<\/td>\nTable 69. Content of an Inter-Domain Request <\/td>\n<\/tr>\n
244<\/td>\nTable 610. Content of an Inter-Domain Response <\/td>\n<\/tr>\n
245<\/td>\n6.4.3 Control Packet Routing <\/td>\n<\/tr>\n
248<\/td>\n6.4.4 Control Packet Reliability <\/td>\n<\/tr>\n
249<\/td>\n6.5 Notification Events
Table 611. Notification Events <\/td>\n<\/tr>\n
250<\/td>\n6.6 Notification Acknowledgement
6.7 Router Enumeration and Initialization <\/td>\n<\/tr>\n
252<\/td>\n6.8 Hot Plug and Hot Unplug Events <\/td>\n<\/tr>\n
254<\/td>\n6.8.1 Router Hot Plug
6.8.2 Router Hot Unplug <\/td>\n<\/tr>\n
255<\/td>\n6.9 Downstream Facing Port Reset
6.10 Timing Parameters
Table 612. Configuration Layer Timing Parameters <\/td>\n<\/tr>\n
256<\/td>\n7 Time Synchronization
7.1 Time Synchronization Architecture
7.1.1 Synchronization Hierarchy <\/td>\n<\/tr>\n
257<\/td>\n7.1.2 Time Sync Parameters
Figure 71. Time Synchronization Hierarchy within a Domain (Informative) <\/td>\n<\/tr>\n
258<\/td>\nFigure 72. Local Time Counter Format
Figure 73. TimeOffsetFromHR Register Format <\/td>\n<\/tr>\n
259<\/td>\n7.2 Time Stamp Measurement
7.2.1 Asymmetry Corrections
Figure 74. FreqOffsetFromHR Register Format
Figure 75. Time Measurement Model for 64\/66b Encoding <\/td>\n<\/tr>\n
260<\/td>\n7.3 Time Sync Protocol
7.3.1 Time Sync Handshake <\/td>\n<\/tr>\n
261<\/td>\nFigure 76. Bi-Directional Time Sync Handshake <\/td>\n<\/tr>\n
262<\/td>\nTable 71. Bidirectional UFP Timeout Values <\/td>\n<\/tr>\n
263<\/td>\nFigure 77. UFP State Machine for Bi-Directional Time Sync Handshake (Recommended)
Table 72. Bidirectional DFP Timeout Values <\/td>\n<\/tr>\n
264<\/td>\nFigure 78. DFP State Machine for Bi-Directional Time Sync Handshake (Recommended) <\/td>\n<\/tr>\n
265<\/td>\nFigure 79. Uni-Directional Time Sync Handshake <\/td>\n<\/tr>\n
266<\/td>\nFigure 710. DFP State Machine for Uni-Directional Time Sync Handshake (Recommended) <\/td>\n<\/tr>\n
267<\/td>\n7.3.2 Inter-Domain Time Sync
Figure 711. UFP State Machine for Uni-Directional Time Sync Handshake (Recommended) <\/td>\n<\/tr>\n
269<\/td>\n7.3.3 Packet Formats
Figure 712. Inter-Domain Time Sync Protocol (Informative) <\/td>\n<\/tr>\n
270<\/td>\nFigure 713. Follow-Up Packet Format
Table 73. Follow-Up Packet Payload <\/td>\n<\/tr>\n
272<\/td>\n7.4 Time Computations
Figure 714. Inter-Domain Time Stamp Packet Format
Table 74. Inter-Domain Time Stamp Packet Payload <\/td>\n<\/tr>\n
273<\/td>\nTable 75. Definition of Variables
Table 76. Index Notation <\/td>\n<\/tr>\n
274<\/td>\n7.4.1 Intra-Domain Equations
Figure 715. Inter-Domain Topology (Informative) <\/td>\n<\/tr>\n
276<\/td>\n7.4.2 Inter-Domain Equations <\/td>\n<\/tr>\n
280<\/td>\n7.4.3 Filtering
Figure 716. Filter Attenuation <\/td>\n<\/tr>\n
281<\/td>\n7.5 Time Synchronization Accuracy Requirements
7.5.1 Paired Measurement
7.5.2 Standalone Measurement
Figure 717. Dynamic Noise Types <\/td>\n<\/tr>\n
282<\/td>\n7.5.3 Measuring Method
Figure 718. Standalone Measurement Points <\/td>\n<\/tr>\n
283<\/td>\n7.5.4 Accuracy Parameters
Figure 719. Time Events
Figure 720. Measuring Method <\/td>\n<\/tr>\n
284<\/td>\n7.6 Software Configuration
7.6.1 Intra-Domain Time Synchronization Setup
7.6.2 Inter-Domain Time Synchronization Setup
7.6.3 Post Time Mechanism
Table 77. Time Synchronization Accuracy Parameters <\/td>\n<\/tr>\n
285<\/td>\n7.6.4 Time Disruption Bit <\/td>\n<\/tr>\n
286<\/td>\n8 Configuration Spaces
8.1 Configuration Fields Access Types
Table 81. Configuration Register Fields Access Types <\/td>\n<\/tr>\n
287<\/td>\n8.2 Configuration Spaces
8.2.1 Router Configuration Space <\/td>\n<\/tr>\n
288<\/td>\nFigure 81. Structure of the Router Configuration Space
Table 82. List of Router Configuration Capabilities <\/td>\n<\/tr>\n
289<\/td>\nTable 83. Router Configuration Space Basic Attributes <\/td>\n<\/tr>\n
296<\/td>\nFigure 82. UUID Format <\/td>\n<\/tr>\n
297<\/td>\nFigure 83. Structure of the TMU Router Configuration Capability <\/td>\n<\/tr>\n
298<\/td>\nTable 84. TMU Router Configuration Capability Fields <\/td>\n<\/tr>\n
303<\/td>\nTable 85. Locked Registers Groups <\/td>\n<\/tr>\n
304<\/td>\nFigure 84. Structure of a Vendor Specific Capability
Figure 85. Structure of a Vendor Specific Extended Capability
Table 86. Vendor Specific Capability Fields <\/td>\n<\/tr>\n
305<\/td>\n8.2.2 Adapter Configuration Space
Table 87. Vendor Specific Extended Capability Fields <\/td>\n<\/tr>\n
306<\/td>\nFigure 86. Structure of the Adapter Configuration Space
Table 88. List of Adapter Configuration Capabilities <\/td>\n<\/tr>\n
307<\/td>\nFigure 87. Basic Configuration Registers of the Adapter Configuration Space
Table 89. Adapter Configuration Space Basic Attributes <\/td>\n<\/tr>\n
311<\/td>\nFigure 88. Structure of the TMU Adapter Configuration Capability
Table 810. Adapter Types <\/td>\n<\/tr>\n
312<\/td>\nTable 811. TMU Adapter Configuration Capability Fields <\/td>\n<\/tr>\n
314<\/td>\nFigure 89. Structure of the Lane Adapter Configuration Capability
Table 812. Contents of the Lane Adapter Configuration Capability <\/td>\n<\/tr>\n
317<\/td>\nFigure 810. Structure of USB4 Port Capability <\/td>\n<\/tr>\n
318<\/td>\nTable 813. USB4 Port Capability Fields <\/td>\n<\/tr>\n
323<\/td>\nFigure 811. Structure of USB3 Adapter Configuration Capability
Table 814. USB3 Adapter Configuration Capability Fields <\/td>\n<\/tr>\n
326<\/td>\nFigure 812. Structure of DP IN Adapter Configuration Capability
Table 815. DP IN Adapter Configuration Capability Fields <\/td>\n<\/tr>\n
333<\/td>\nFigure 813. Structure of DP OUT Adapter Configuration Capability
Table 816. DP OUT Adapter Configuration Capability Fields <\/td>\n<\/tr>\n
338<\/td>\nFigure 814. Structure of PCIe Adapter Configuration Capability
Table 817. PCIe Adapter Configuration Capability Fields <\/td>\n<\/tr>\n
339<\/td>\n8.2.3 Path Configuration Space
Figure 815. Structure of Path 0 Entry Configuration Space <\/td>\n<\/tr>\n
340<\/td>\nFigure 816. Structure of Path Entry \u2018n\u2019 in Path Configuration Space at Lane Adapter
Table 818. Contents of Path 0 Entry <\/td>\n<\/tr>\n
341<\/td>\nTable 819. Contents of Path Entry in Path Configuration Space at Lane Adapter <\/td>\n<\/tr>\n
342<\/td>\nFigure 817. Structure of Path Entry \u2018n\u2019 in Path Configuration Space of a Protocol Adapter
Table 820. Contents of Path Entry in Path Configuration Space of a Protocol Adapter <\/td>\n<\/tr>\n
345<\/td>\n8.2.4 Counters Configuration Space
Figure 818. Configuration of a Path <\/td>\n<\/tr>\n
346<\/td>\nFigure 819. Structure of the Counters Configuration Space
Table 821. Counter Set Fields <\/td>\n<\/tr>\n
347<\/td>\n8.3 Operations
8.3.1 Router Operations <\/td>\n<\/tr>\n
348<\/td>\nTable 822. List of Router Operations <\/td>\n<\/tr>\n
349<\/td>\nTable 823. Query DP Resource Availability Operation Metadata
Table 824. Query DP Resource Availability Completion Metadata and Status
Table 825. Allocate DP Resource Operation Metadata <\/td>\n<\/tr>\n
350<\/td>\nTable 826. Allocate DP Resource Completion Metadata and Status
Table 827. De-Allocate DP Resource Operation Metadata
Table 828. De-Allocate DP Resource Completion Metadata and Status <\/td>\n<\/tr>\n
351<\/td>\nTable 829. NVM Set Offset Operation Metadata <\/td>\n<\/tr>\n
352<\/td>\nTable 830. NVM Set Offset Completion Metadata and Status
Table 831. NVM Write Operation Data <\/td>\n<\/tr>\n
353<\/td>\nTable 832. NVM Write Completion Status
Table 833. NVM Authenticate Write Completion Status <\/td>\n<\/tr>\n
354<\/td>\nTable 834. NVM Read Operation Metadata
Table 835. NVM Read Router Completion Metadata
Table 836. NVM Read Router Completion Data <\/td>\n<\/tr>\n
355<\/td>\nTable 837. DROM Read Router Operation Metadata
Table 838. DROM Read Router Completion Metadata and Status
Table 839. DROM Read Router Completion Data <\/td>\n<\/tr>\n
356<\/td>\nTable 840. Get NVM Sector Size Completion Metadata and Status <\/td>\n<\/tr>\n
357<\/td>\nTable 841. Get PCIe Downstream Entry Mapping Completion Metadata and Status
Table 842. Get PCIe Downstream Entry Mapping Completion Data <\/td>\n<\/tr>\n
358<\/td>\nTable 843. Get Capabilities Operation Metadata
Table 844. Get Capabilities Operation Completion Metadata and Status <\/td>\n<\/tr>\n
359<\/td>\nFigure 820. Get Capabilities Operation Data Response for Capability Index 0
Table 845. List of Capabilities <\/td>\n<\/tr>\n
360<\/td>\nTable 846. Set Capabilities Operation Metadata
Table 847. List of Capabilities
Table 848. Set Capabilities Operation Completion Status <\/td>\n<\/tr>\n
361<\/td>\nTable 849. Buffer Allocation Request Router Completion Status and Metadata
Table 850. Buffer Allocation Request Router Completion Data DW Structure <\/td>\n<\/tr>\n
362<\/td>\nTable 851. Get Container-ID Router Completion Status
Table 852. Get Container-ID Router Completion Data DW Structure
Table 853. Block Sideband Port Operation Completion Status <\/td>\n<\/tr>\n
363<\/td>\n8.3.2 Port Operations
Table 854. Unblock Sideband Port Operation Completion Status <\/td>\n<\/tr>\n
365<\/td>\nTable 855. List of Port Operations <\/td>\n<\/tr>\n
368<\/td>\nTable 856. SET_TX_COMPLIANCE Operation Metadata <\/td>\n<\/tr>\n
370<\/td>\nTable 857. SET_RX_COMPLIANCE Operation Metadata <\/td>\n<\/tr>\n
371<\/td>\nTable 858. START_BER_TEST Operation Metadata
Table 859. END_BER_TEST Operation Metadata <\/td>\n<\/tr>\n
372<\/td>\nTable 860. END_BER_TEST Completion Data <\/td>\n<\/tr>\n
373<\/td>\nTable 861. END_BURST_TEST Operation Metadata
Table 862. END_BURST_TEST Completion Data <\/td>\n<\/tr>\n
374<\/td>\nTable 863. READ_BURST_TEST Operation Metadata
Table 864. READ_BURST_TEST Completion Data <\/td>\n<\/tr>\n
375<\/td>\nTable 865. ENTER_EI_TEST Operation Metadata
Table 866. ROUTER_OFFLINE_MODE Operation Metadata <\/td>\n<\/tr>\n
377<\/td>\nTable 867. READ_LANE_MARGIN_CAP Completion Data <\/td>\n<\/tr>\n
379<\/td>\nTable 868. RUN_HW_LANE_MARGINING Operation Metadata
Table 869. Contents Selection for RUN_HW_LANE_MARGINING Completion Data <\/td>\n<\/tr>\n
380<\/td>\nTable 870. RUN_HW_LANE_MARGINING Completion Data <\/td>\n<\/tr>\n
383<\/td>\nTable 871. RUN_SW_LANE_MARGINING Operation Metadata <\/td>\n<\/tr>\n
384<\/td>\nTable 872. RUN_SW_LANE_MARGINING Completion Data <\/td>\n<\/tr>\n
385<\/td>\nTable 873. READ_SW_ MARGIN_ERR Completion Metadata <\/td>\n<\/tr>\n
386<\/td>\n9 USB3 Tunneling <\/td>\n<\/tr>\n
387<\/td>\n9.1 USB3 Adapter Layer
9.1.1 Encapsulation <\/td>\n<\/tr>\n
388<\/td>\nTable 91. PDF Values for USB3 Tunneling Packets
Table 92. LFPS Tunneled Packet Payload <\/td>\n<\/tr>\n
389<\/td>\nFigure 91. LFPS Tunneled Packet Format <\/td>\n<\/tr>\n
392<\/td>\nFigure 92. Ordered Set Tunneled Packet Format
Table 93. Ordered Set Tunneled Packet Payload <\/td>\n<\/tr>\n
393<\/td>\nFigure 93. Link Command Tunneled Packet Format <\/td>\n<\/tr>\n
394<\/td>\nFigure 94. Tunneled ITP Packet Format <\/td>\n<\/tr>\n
395<\/td>\nFigure 95. Structure of an Unsegmented USB3 Data Packet <\/td>\n<\/tr>\n
396<\/td>\nFigure 96. Segmentation of a USB3 Data Packet <\/td>\n<\/tr>\n
397<\/td>\n9.1.2 Bandwidth Negotiation <\/td>\n<\/tr>\n
398<\/td>\nFigure 97. Bandwidth Negotiation by the Internal Host Controller <\/td>\n<\/tr>\n
399<\/td>\n9.1.3 Timing Parameters
9.2 Internal USB3 Device
Figure 98. Bandwidth Negotiation by the Connection Manager
Table 94. USB3 Adapter Timing Parameters <\/td>\n<\/tr>\n
400<\/td>\n9.2.1 Link Layer
Table 95. USB3 Timers and Timeout Values <\/td>\n<\/tr>\n
401<\/td>\n9.2.2 USB3 Protocol Layer
9.2.3 Descriptors
9.3 Paths
9.3.1 Path Setup
9.3.2 Path Teardown <\/td>\n<\/tr>\n
403<\/td>\n10 DisplayPort\u2122 Tunneling
10.1 DP Adapter Protocol Stack <\/td>\n<\/tr>\n
404<\/td>\n10.1.1 Transport Layer
10.1.2 Protocol Adapter Layer
10.1.3 DP Physical Layer
10.2 DP Adapter States
Figure 101. DP Adapter Protocol Stack Layers <\/td>\n<\/tr>\n
405<\/td>\n10.2.1 Reset
10.2.2 Present
Figure 102. DP Adapter State Machine <\/td>\n<\/tr>\n
406<\/td>\n10.2.3 Plugged
10.2.4 Paired
10.3 Interfaces
10.3.1 DisplayPort <\/td>\n<\/tr>\n
407<\/td>\nTable 101. DisplayPort Modes Of Operation Over DisplayPort Tunneling <\/td>\n<\/tr>\n
408<\/td>\n10.3.2 Programming Model
Figure 103. DP Adapter Path Directions
Table 102. Recommended Path Parameters <\/td>\n<\/tr>\n
409<\/td>\n10.3.3 Hot Plug and Hot Removal Events <\/td>\n<\/tr>\n
410<\/td>\nFigure 104. DP Stream Resource Mapping Examples
Table 103. DP Stream Resource Allocation Commands <\/td>\n<\/tr>\n
411<\/td>\n10.3.4 DisplayPort Over USB4 Fabric
Table 104. AUX Path Tunneled Packet Types
Table 105. Main-Link Path Tunneled Packet Types <\/td>\n<\/tr>\n
412<\/td>\nFigure 105. AUX Channel Framing
Figure 106. AUX Packet Format <\/td>\n<\/tr>\n
413<\/td>\nFigure 107. AUX Packet Example <\/td>\n<\/tr>\n
414<\/td>\nFigure 108. HPD Packet Format
Figure 109. SET_CONFIG Packet Format <\/td>\n<\/tr>\n
416<\/td>\nTable 106. SET_CONFIG Message <\/td>\n<\/tr>\n
418<\/td>\n10.4 System Flows
10.4.1 Connection Manager Discovery
Figure 1010. ACK Packet Format <\/td>\n<\/tr>\n
419<\/td>\n10.4.2 Path Configuration
Figure 1011. Power On to HPD Sequence <\/td>\n<\/tr>\n
421<\/td>\nTable 107. DisplayPort Required Bandwidth (Gbps) <\/td>\n<\/tr>\n
422<\/td>\n10.4.3 HPD Event Propagation <\/td>\n<\/tr>\n
423<\/td>\n10.4.4 AUX Request and Response Handling
Table 108. HPD Event Propagation Delay Requirement <\/td>\n<\/tr>\n
424<\/td>\nFigure 1012. Target AUX Transaction Flow <\/td>\n<\/tr>\n
425<\/td>\nFigure 1013. Snoop AUX Transaction Flow <\/td>\n<\/tr>\n
426<\/td>\nTable 109. DPCD Internal Addresses <\/td>\n<\/tr>\n
427<\/td>\nFigure 1014. DP IN Adapter AUX Handling State Machine
Table 1010. DP IN Adapter AUX Handling State Machine <\/td>\n<\/tr>\n
430<\/td>\nFigure 1015. AUX Timing
Table 1011. AUX Delay Requirements
Table 1012. Aggregated DisplayPort Capabilities <\/td>\n<\/tr>\n
432<\/td>\n10.4.5 DP Adapters Init Flow
10.4.6 Source Discovery
Figure 1016. Example DP Source Discovery Sequence <\/td>\n<\/tr>\n
433<\/td>\nTable 1013. DP Adapter Operation Mode Transitions <\/td>\n<\/tr>\n
434<\/td>\n10.4.7 Down-Spread Control
10.4.8 Stream Mode Set
10.4.9 DSC and FEC Enable <\/td>\n<\/tr>\n
435<\/td>\n10.4.10 DP Link Training <\/td>\n<\/tr>\n
437<\/td>\nFigure 1017. DP Link Training \u2013 LTTPR CR_DONE <\/td>\n<\/tr>\n
438<\/td>\nFigure 1018. DP Link Training \u2013 LTTPR \u2013 EQ Phase <\/td>\n<\/tr>\n
439<\/td>\nFigure 1019. DP Link Training \u2013 DPRX \u2013 CR_DONE Phase <\/td>\n<\/tr>\n
440<\/td>\nFigure 1020. DP Link Training \u2013 DPRX \u2013 EQ Phase <\/td>\n<\/tr>\n
442<\/td>\n10.4.11 Power States Set
10.4.12 DP Main-Link Disable <\/td>\n<\/tr>\n
443<\/td>\n10.4.13 Link-Init
10.4.14 DP PHY Testability <\/td>\n<\/tr>\n
444<\/td>\n10.5 High Speed Tunneling <\/td>\n<\/tr>\n
445<\/td>\n10.5.1 SST Tunneling
Figure 1021. Main-Link SST Stream to Tunneled Packets <\/td>\n<\/tr>\n
446<\/td>\nFigure 1022. TU Set Packing for a 4-Lane Main-Link <\/td>\n<\/tr>\n
447<\/td>\nFigure 1023. TU Set Packing for a 2-Lane Main-Link <\/td>\n<\/tr>\n
448<\/td>\nFigure 1024. TU Set Packing for a 1-Lane Main-Link <\/td>\n<\/tr>\n
449<\/td>\nFigure 1025. EOC Symbol Packing Example
Figure 1026. TU Set Header Format <\/td>\n<\/tr>\n
451<\/td>\nFigure 1027. Video Data Packet Format
Figure 1028. MSA Header Format <\/td>\n<\/tr>\n
452<\/td>\nFigure 1029. MSA Packet Format <\/td>\n<\/tr>\n
453<\/td>\nFigure 1030. Blank Start Header Format <\/td>\n<\/tr>\n
454<\/td>\nFigure 1031. Blank Start Packet Format
Table 1014. Blank Start Control Link Symbols Mapping <\/td>\n<\/tr>\n
455<\/td>\nFigure 1032. Secondary TU Header Format <\/td>\n<\/tr>\n
457<\/td>\nFigure 1033. Tunneled Secondary Data Path Format <\/td>\n<\/tr>\n
458<\/td>\nFigure 1034. Secondary Data to Secondary TUs Examples <\/td>\n<\/tr>\n
459<\/td>\nTable 1015. Fill Count Prev_Factor <\/td>\n<\/tr>\n
460<\/td>\nFigure 1035. Non-Secondary Data Packet Fill Count Examples <\/td>\n<\/tr>\n
461<\/td>\n10.5.2 MST Tunneling
Figure 1036. Secondary Data Packet Fill Count Examples <\/td>\n<\/tr>\n
462<\/td>\nFigure 1037. Sub-MTP TU Structures
Figure 1038. Sub-MTP TU Header Format
Table 1016. Slot Zero Sub-MTP TU Header Types <\/td>\n<\/tr>\n
463<\/td>\nTable 1017. Non-Slot Zero Sub-MTP TU Header Types
Table 1018. Slot Zero Sub-MTP TU Packet Rules <\/td>\n<\/tr>\n
464<\/td>\nTable 1019. Non- Zero Slot Sub-MTP TU Packet Rules <\/td>\n<\/tr>\n
465<\/td>\nTable 1020. K-Code Index Nibble in Parameter Byte <\/td>\n<\/tr>\n
466<\/td>\nFigure 1039. Sub-MTP TU 4-Lane Mapping
Figure 1040. Sub-MTP TU 2-Lane Mapping <\/td>\n<\/tr>\n
467<\/td>\nFigure 1041. Sub-MTP TU 1-Lane Mapping
Figure 1042. Unallocated Sequence, 1-Lane <\/td>\n<\/tr>\n
468<\/td>\nFigure 1043. Shifting SR, 1-Lane
Figure 1044. ACT Sequence, 1-Lane <\/td>\n<\/tr>\n
469<\/td>\nFigure 1045. SF and VCPF Sequence 4-Lane <\/td>\n<\/tr>\n
470<\/td>\n10.5.3 FEC
Figure 1046. MST Packet Format <\/td>\n<\/tr>\n
472<\/td>\n10.5.4 DP OUT Adapter Buffer
Figure 1047. FEC_DECODE Packet Format
Figure 1048. FEC Command Format <\/td>\n<\/tr>\n
473<\/td>\nFigure 1049. Active Video to Blanking <\/td>\n<\/tr>\n
474<\/td>\n10.5.5 HDCP
10.6 DP Link Clock Sync <\/td>\n<\/tr>\n
475<\/td>\n10.6.1 Synchronization Method
Figure 1050: Adjust PLL Event Occurrence <\/td>\n<\/tr>\n
476<\/td>\nFigure 1051. Lifetime Counter Format <\/td>\n<\/tr>\n
477<\/td>\nFigure 1052. Filtered Lifetime Counter Logic Concept
Table 1021. FLC Calculation Examples <\/td>\n<\/tr>\n
478<\/td>\nFigure 1053. DP Clock Sync Packet Format <\/td>\n<\/tr>\n
479<\/td>\n10.6.2 DP Adapter Requirements
Figure 1054. DP Clock Sync Packet Example <\/td>\n<\/tr>\n
480<\/td>\n10.7 DP BW Allocation Mode
10.7.1 DP BW Allocation Mode Enablement <\/td>\n<\/tr>\n
481<\/td>\n10.7.2 Interaction with DPTX
Table 1022. DPCD Bandwidth Allocation Registers <\/td>\n<\/tr>\n
482<\/td>\nTable 1023. DP IN Adapter Configuration Space Mapping <\/td>\n<\/tr>\n
483<\/td>\nFigure 1055: DP IN Adapter Interaction with DPTX During DP BW Allocation <\/td>\n<\/tr>\n
484<\/td>\n10.7.3 Interaction with the Connection Manager <\/td>\n<\/tr>\n
485<\/td>\nFigure 1056: DP BW Allocation Interaction with Connection Manager <\/td>\n<\/tr>\n
486<\/td>\n10.8 Timing Parameters <\/td>\n<\/tr>\n
487<\/td>\n11 PCI Express Tunneling <\/td>\n<\/tr>\n
488<\/td>\n11.1 PCIe Adapter Layer
11.1.1 Encapsulation
Table 111. PDF Values for PCIe Tunneled Packets <\/td>\n<\/tr>\n
489<\/td>\nFigure 111. Tunneled PCIe TLP <\/td>\n<\/tr>\n
490<\/td>\nFigure 112. Tunneled PTM Example
Table 112. TLP Pre-Header <\/td>\n<\/tr>\n
491<\/td>\nFigure 113. Tunneled PCIe DLLP <\/td>\n<\/tr>\n
492<\/td>\nFigure 114. PCIe DLLP and TLP Tunneled Packet Payload <\/td>\n<\/tr>\n
493<\/td>\nTable 113. TS Ordered Sets
Table 114. Electrical Idle Ordered Sets <\/td>\n<\/tr>\n
495<\/td>\n11.1.2 USB4 Hot-Plug
11.2 Internal PCIe Ports
11.2.1 PCIe Physical Layer Logical Sub-block <\/td>\n<\/tr>\n
496<\/td>\n11.2.2 PCIe Data Link Layer
11.2.3 PCIe Transaction Layer <\/td>\n<\/tr>\n
497<\/td>\n11.2.4 PCIe Link Timers (Informative) <\/td>\n<\/tr>\n
498<\/td>\n11.2.5 Precision Time Measurement (PTM) Mechanism
Table 115. PCIe Link Timer Ranges <\/td>\n<\/tr>\n
499<\/td>\nFigure 115: Example of PTM Relationships <\/td>\n<\/tr>\n
500<\/td>\nFigure 116: PTM ResponseD Message <\/td>\n<\/tr>\n
502<\/td>\nFigure 117: TMU to PTM Parameters Illustration <\/td>\n<\/tr>\n
503<\/td>\n11.2.6 Timing Parameters
11.3 Paths
11.3.1 Path Set-Up
11.3.2 Path Tear-Down
Table 116. PCIe Adapter Timing Parameters <\/td>\n<\/tr>\n
504<\/td>\n12 Host Interface <\/td>\n<\/tr>\n
505<\/td>\n12.1 Descriptor Ring Mode
12.1.1 DW, Byte, and Bit Order <\/td>\n<\/tr>\n
506<\/td>\n12.1.2 Raw Mode
12.1.3 Frame Mode <\/td>\n<\/tr>\n
507<\/td>\nFigure 121. Segmentation of a Frame
Table 121. Frame Mode Tunneled Packet Format <\/td>\n<\/tr>\n
508<\/td>\n12.2 End-to-End (E2E) Flow Control
12.2.1 E2E Flow Control Packets <\/td>\n<\/tr>\n
509<\/td>\nFigure 122. Example of Forwarding an E2E Credit Grant Packet
Figure 123. E2E Credit Grant \/ Sync Packet Format
Table 122. E2E Credit Grant Packet Header
Table 123. E2E Credit Grant Packet Payload <\/td>\n<\/tr>\n
510<\/td>\n12.2.2 Flow Control Rules
Table 124. E2E Credit Sync Packet Header
Table 125. E2E Credit Sync Packet Payload <\/td>\n<\/tr>\n
513<\/td>\n12.3 Transmit Interface
12.3.1 Transmit Descriptor Structure
Figure 124. Transmit Descriptor Structure
Table 126. Transmit Descriptor Contents <\/td>\n<\/tr>\n
514<\/td>\n12.3.2 Transmit Flow <\/td>\n<\/tr>\n
516<\/td>\n12.4 Receive Interface
12.4.1 Receive Descriptor Structure
Figure 125. Receive Descriptor Structure (Posted by Host)
Table 127. Receive Descriptor Contents (Posted by Host) <\/td>\n<\/tr>\n
517<\/td>\nFigure 126. Receive Descriptor Structure (Posted by Host Interface Adapter Layer)
Table 128. Receive Descriptor Contents (Posted by Host Interface Adapter Layer) <\/td>\n<\/tr>\n
518<\/td>\n12.4.2 Receive Flow <\/td>\n<\/tr>\n
520<\/td>\n12.5 Interrupts
12.5.1 Interrupt Causes
12.5.2 Interrupt Masks
12.5.3 Interrupt Vectors
12.5.4 Interrupt Moderation <\/td>\n<\/tr>\n
521<\/td>\n12.6 Programming Interface
Figure 127. Interrupt Moderation <\/td>\n<\/tr>\n
522<\/td>\n12.6.1 Access Types
12.6.2 Registers Summary
Table 129. Access Types
Table 1210. Summary of Memory BAR Registers <\/td>\n<\/tr>\n
523<\/td>\n12.6.3 Registers Description
Table 1211. Host Interface Capabilities Register <\/td>\n<\/tr>\n
524<\/td>\nTable 1212. Host Interface Reset Register
Table 1213. Host Interface Control Register
Table 1214. Host Interface CL1 Enable
Table 1215. Host Interface CL2 Enable <\/td>\n<\/tr>\n
525<\/td>\nTable 1216. Base Address Low Register
Table 1217. Base Address High Register
Table 1218. Producer and Consumer Indexes Register <\/td>\n<\/tr>\n
526<\/td>\nTable 1219. Ring Size Register <\/td>\n<\/tr>\n
527<\/td>\nTable 1220. Ring Control Register
Table 1221. Base Address Low Register
Table 1222. Base Address High Register <\/td>\n<\/tr>\n
528<\/td>\nTable 1223. Producer and Consumer Indexes Register
Table 1224. Ring Size Register <\/td>\n<\/tr>\n
529<\/td>\nTable 1225. Ring Control Register <\/td>\n<\/tr>\n
530<\/td>\nFigure 128. Structure of the Interrupt Status Registers
Table 1226. PDF Bit Masks Register <\/td>\n<\/tr>\n
531<\/td>\nTable 1227. Interrupt Status
Table 1228. Interrupt Status Clear
Table 1229. Interrupt Status Set <\/td>\n<\/tr>\n
532<\/td>\nTable 1230. Interrupt Mask
Table 1231. Interrupt Mask Clear
Table 1232. Interrupt Mask Set
Table 1233. Interrupt Throttling Rate (ITR) <\/td>\n<\/tr>\n
533<\/td>\nFigure 129. Structure of the Interrupt Vector Allocation Registers (IVAR)
Table 1234. Interrupt Vector Allocation (IVAR) <\/td>\n<\/tr>\n
534<\/td>\nFigure 1210. Structure of the Receive Ring Vacancy Control Register
Table 1235. Receive Ring Vacancy Control
Table 1236. Receive Ring Vacancy Status <\/td>\n<\/tr>\n
535<\/td>\n12.7 Timing Parameters
13 Interoperability with Thunderbolt\u2122 3 (TBT3) Systems
13.1 Electrical Layer
Table 1237. Host Interface Timing Parameters
Table 131. Thunderbolt 3 Parameters <\/td>\n<\/tr>\n
536<\/td>\n13.2 Logical Layer
13.2.1 Sideband Channel
Figure 131. Bidirectional Re-timer Topology <\/td>\n<\/tr>\n
537<\/td>\nTable 132. TBT3 LT Transaction Types
Table 133. STX Symbol <\/td>\n<\/tr>\n
538<\/td>\nFigure 132. Bounce Mechanism
Table 134. Contents of Byte 2 in a Broadcast RT Transaction <\/td>\n<\/tr>\n
539<\/td>\nTable 135. SB Registers
Table 136. SB Registers Fields <\/td>\n<\/tr>\n
540<\/td>\nTable 137. Lane Attributes <\/td>\n<\/tr>\n
544<\/td>\n13.2.2 Logical Layer State Machine <\/td>\n<\/tr>\n
545<\/td>\n13.2.3 USB4 Link Operation
13.2.4 Sleep and Wake
Table 138. TS1 and TS2 Ordered Set Structure <\/td>\n<\/tr>\n
546<\/td>\nTable 139. Router State Retained During Sleep <\/td>\n<\/tr>\n
547<\/td>\n13.2.5 Timing Parameters
13.3 Transport Layer
13.3.1 Adapter Numbering Rules
13.3.2 Maximum HopID
13.3.3 Connectivity Rules
Table 1310. Logical Layer Timing Parameters <\/td>\n<\/tr>\n
548<\/td>\n13.3.4 Buffer Allocation
13.4 Configuration Layer
13.4.1 Router Enumeration
13.4.2 Notification Packet
13.4.3 Bit Banging Interface
Table 1311. Buffer Allocation by TBT3 Connection Manager <\/td>\n<\/tr>\n
549<\/td>\n13.4.4 Control Packet Routing <\/td>\n<\/tr>\n
550<\/td>\n13.5 Time Synchronization
13.6 Configuration Spaces <\/td>\n<\/tr>\n
551<\/td>\n13.6.1 Router Configuration Space
Figure 133. Structure of the Vendor Specific 1 Capability
Table 1312. Configuration Register Fields Access Types
Table 1313. List of TBT3-Compatible Router Configuration Capabilities <\/td>\n<\/tr>\n
552<\/td>\nTable 1314. Vendor Specific 1 Capability Fields <\/td>\n<\/tr>\n
556<\/td>\nFigure 134. Structure of the Vendor Specific 3 Capability
Table 1315. Vendor Specific 3 Capability Fields <\/td>\n<\/tr>\n
558<\/td>\nFigure 135. Structure of the Vendor Specific 4 Capability
Table 1316. Vendor Specific 4 Capability Fields <\/td>\n<\/tr>\n
559<\/td>\nFigure 136. Structure of the Vendor Specific Extended 6 Capability <\/td>\n<\/tr>\n
560<\/td>\nFigure 137. Example Vendor Specific Extended 6 Capability
Figure 138. Structure of the Common Region
Table 1317. Common Region Fields <\/td>\n<\/tr>\n
562<\/td>\nFigure 139. Structure of a USB4 Port Region
Table 1318. USB4 Port Region Fields <\/td>\n<\/tr>\n
566<\/td>\n13.6.2 Adapter Configuration Space
Table 1319. Adapter Configuration Space Basic Attributes <\/td>\n<\/tr>\n
567<\/td>\n13.7 PCI Express Tunneling
13.7.1 PCIe Power Management
Table 1320. USB4 Port Capability Fields <\/td>\n<\/tr>\n
568<\/td>\n13.8 DisplayPort Tunneling
13.8.1 AUX Handling <\/td>\n<\/tr>\n
569<\/td>\n13.8.2 IRQ Handling
13.8.3 Connection Manager Discovery <\/td>\n<\/tr>\n
570<\/td>\n13.8.4 Sink Count Read
13.8.5 Power States Set
13.8.6 DisplayPort Link Training <\/td>\n<\/tr>\n
571<\/td>\nFigure 1310. DP IN Adapter Link Training State Machine
Table 1321. DP IN Adapter Link Training State Machine Transition Table <\/td>\n<\/tr>\n
572<\/td>\nFigure 1311. DP OUT Adapter Link Training State Machine
Table 1322. DP OUT Adapter Link Training State Machine Transition Table <\/td>\n<\/tr>\n
573<\/td>\n13.9 USB3 Functionality <\/td>\n<\/tr>\n
574<\/td>\nFigure 1312. Example of a USB4-Based Dock with an Internal Host Controller <\/td>\n<\/tr>\n
575<\/td>\n13.10 Host-to-Host Tunneling
A Verification of CRC, Scrambling, and FEC Calculations
A.1 Transport Layer Packet HEC
A.2 Control Packet CRC
Figure A1. Examples of Transport Layer Packet HEC Calculation <\/td>\n<\/tr>\n
576<\/td>\nA.3 Sideband Channel AT Transaction CRC
Table A1. Examples of Control Packet CRC Calculation
Table A2. Example of a Read Command
Table A3. Example of a Write Command <\/td>\n<\/tr>\n
577<\/td>\nA.4 Scrambler
A.5 Logical Layer RS-FEC
Table A4. Examples of Scrambler Computations
Table A5. Example 1 \u2013 RS-FEC Block <\/td>\n<\/tr>\n
579<\/td>\nTable A6. Example 2 \u2013 RS-FEC Block <\/td>\n<\/tr>\n
580<\/td>\nTable A7. Example 3 \u2013 RS-FEC Block <\/td>\n<\/tr>\n
581<\/td>\nTable A8. Example 4 \u2013 RS-FEC Block <\/td>\n<\/tr>\n
582<\/td>\nA.6 USB3 Tunneling CRC <\/td>\n<\/tr>\n
583<\/td>\nA.7 Host Interface Frame CRC
Figure A2. Examples of USB3 Tunneling Calculations <\/td>\n<\/tr>\n
588<\/td>\nA.8 ECC Examples
Figure A3. Example of a Credit Grant Record
Figure A4. Example of an HPD Packet Payload
Figure A5. Example of a SET_CONFIG Packet Payload <\/td>\n<\/tr>\n
589<\/td>\nB Summary of Transport Layer Packets
Figure A6. Example of TU Set Header
Figure A7. Example of a Sub-MTP TU Header
Figure A8. Example of an E2E Credit Sync Packet Payload
Table B1. Transport Layer Packet Summary <\/td>\n<\/tr>\n
590<\/td>\nC Examples of Link Power Management Flows
C.1 Entry to Low Power States
C.1.1 Successful Entry to CL2 State <\/td>\n<\/tr>\n
591<\/td>\nC.1.2 Successful Entry to CL0s State
Figure C1. Successful Entry to CL2 State
Figure C2. Successful Entry to CL0s State <\/td>\n<\/tr>\n
592<\/td>\nC.1.3 Rejection to Enter CL2 State
C.1.4 Concurrent Requests to Enter Low Power State
Figure C3. Failure to Enter CL2 State <\/td>\n<\/tr>\n
593<\/td>\nC.1.5 CL2_REQ Ordered Sets are Not Received
Figure C4. Concurrent Requests to Enter CL2 State <\/td>\n<\/tr>\n
594<\/td>\nC.1.6 CL2_REQ Ordered Sets are Partially Received
Figure C5. Error in CL2_REQ Ordered Sets
Figure C6. CL2_REQ Ordered Sets are Partially Received <\/td>\n<\/tr>\n
595<\/td>\nC.1.7 Error in CL2_ACK Ordered Sets
Figure C7. Errors in CL2_REQ Reception and CL_NACK Response <\/td>\n<\/tr>\n
596<\/td>\nC.1.8 Error in CL_OFF Ordered Sets
Figure C8. Error in CL2_ACK Ordered Sets
Figure C9. Error in CL_OFF Ordered Sets <\/td>\n<\/tr>\n
597<\/td>\nC.2 Exit from Low Power States
C.2.1 Example: Exit from CL0s State <\/td>\n<\/tr>\n
598<\/td>\nFigure C10. CL0s Exit <\/td>\n<\/tr>\n
599<\/td>\nC.2.2 Example: Exit from CL2 (or CL1) State <\/td>\n<\/tr>\n
600<\/td>\nFigure C11. CL2 (or CL1) Exit <\/td>\n<\/tr>\n
601<\/td>\nD Serial Time Link Protocol (STLP)
D.1 Time Synchronization <\/td>\n<\/tr>\n
602<\/td>\nD.2 Serial Time Link Packet Format
Figure D1. Pulse Width Modulation
Figure D2. Serial Time Link Packet Structure <\/td>\n<\/tr>\n
603<\/td>\nFigure D3. Serial Time Link Packet Format
Table D1. Serial Time Link Packet Fields <\/td>\n<\/tr>\n
604<\/td>\nFigure D4. TMU_CLK_OUT and TMU_CLK_IN Parameters <\/td>\n<\/tr>\n
605<\/td>\nD.3 TMU_CLK_OUT and TMU_CLK_IN
Figure D5. Definition of TCOJTR
Table D2. TMU_CLK_OUT and TMU_CLK_IN Specifications <\/td>\n<\/tr>\n
606<\/td>\nE Ingress Buffer Space
E.1 Target Bandwidth Buffer Calculation
E.1.1 Example for USB3 Tunneling Ingress Buffer Calculation <\/td>\n<\/tr>\n
607<\/td>\nE.2 Ingress Buffers Calculation for DP Main Path <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Universal Serial Bus interfaces for data and power – Universal Serial Bus 4 \u2122 Specification<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2022<\/td>\n608<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":416362,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[631,2641],"product_tag":[],"class_list":{"0":"post-416353","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-33-120-20","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/416353","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/416362"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=416353"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=416353"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=416353"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}