{"id":420662,"date":"2024-10-20T06:32:16","date_gmt":"2024-10-20T06:32:16","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iec-62014-42015-2\/"},"modified":"2024-10-26T12:13:54","modified_gmt":"2024-10-26T12:13:54","slug":"bs-iec-62014-42015-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iec-62014-42015-2\/","title":{"rendered":"BS IEC 62014-4:2015"},"content":{"rendered":"

This standard describes an eXtensible Markup Language (XML) schema1<\/sup> for meta-data documenting intellectual property<\/i> (IP) used in the development, implementation, and verification of electronic systems and an application programming interface<\/i> (API) to provide tool access to the meta-data. This schema provides a standard method to document IP that is compatible with automated integration techniques.The API provides a standard method for linking tools into a system development<\/i> framework, enabling a more flexible, optimized development environment. Tools compliant with this standard will be able to interpret, configure, integrate, and manipulate IP blocks that comply with the IP meta-data description. The standard is based on version 1.4 IP-XACT of The SPIRIT Consortium. The standard is independent of any specific design processes. It does not cover those behavioral characteristics of the IP that are not relevant to integration.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
4<\/td>\nContents <\/td>\n<\/tr>\n
12<\/td>\nIntroduction
\n <\/td>\n<\/tr>\n
15<\/td>\n1.2 Purpose
1.3 Design environment <\/td>\n<\/tr>\n
19<\/td>\n1.4 IP-XACT Enabled implementations <\/td>\n<\/tr>\n
20<\/td>\n1.5 Conventions used <\/td>\n<\/tr>\n
25<\/td>\n1.6 Use of color in this standard
1.7 Contents of this standard <\/td>\n<\/tr>\n
26<\/td>\n2. Normative references <\/td>\n<\/tr>\n
28<\/td>\n3. Definitions, acronyms, and abbreviations
3.1 Definitions <\/td>\n<\/tr>\n
34<\/td>\n3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n
36<\/td>\n4. Interoperability use model
4.1 Roles and responsibilities <\/td>\n<\/tr>\n
37<\/td>\n4.2 IP-XACT IP exchange flows <\/td>\n<\/tr>\n
40<\/td>\n5. Interface definition descriptions
5.1 Definition descriptions
5.2 Bus definition <\/td>\n<\/tr>\n
43<\/td>\n5.3 Abstraction definition <\/td>\n<\/tr>\n
44<\/td>\n5.4 Ports <\/td>\n<\/tr>\n
45<\/td>\n5.5 Wire ports <\/td>\n<\/tr>\n
47<\/td>\n5.6 Qualifiers <\/td>\n<\/tr>\n
49<\/td>\n5.7 Wire port group <\/td>\n<\/tr>\n
51<\/td>\n5.8 Wire port mode constraints <\/td>\n<\/tr>\n
52<\/td>\n5.9 Wire port mirrored-mode constraints <\/td>\n<\/tr>\n
54<\/td>\n5.10 Transactional ports <\/td>\n<\/tr>\n
56<\/td>\n5.11 Transactional port group <\/td>\n<\/tr>\n
57<\/td>\n5.12 Extending bus and abstraction definitions <\/td>\n<\/tr>\n
60<\/td>\n5.13 Clock and reset handling <\/td>\n<\/tr>\n
62<\/td>\n6. Component descriptions
6.1 Component <\/td>\n<\/tr>\n
65<\/td>\n6.2 Interfaces
6.3 Interface interconnections <\/td>\n<\/tr>\n
67<\/td>\n6.4 Complex interface interconnections <\/td>\n<\/tr>\n
69<\/td>\n6.5 Bus interfaces <\/td>\n<\/tr>\n
80<\/td>\n6.6 Component channels <\/td>\n<\/tr>\n
82<\/td>\n6.7 Address spaces <\/td>\n<\/tr>\n
94<\/td>\n6.8 Memory maps <\/td>\n<\/tr>\n
110<\/td>\n6.9 Remapping <\/td>\n<\/tr>\n
115<\/td>\n6.10 Registers <\/td>\n<\/tr>\n
133<\/td>\n6.11 Models <\/td>\n<\/tr>\n
164<\/td>\n6.12 Component generators <\/td>\n<\/tr>\n
166<\/td>\n6.13 File sets <\/td>\n<\/tr>\n
178<\/td>\n6.14 Choices <\/td>\n<\/tr>\n
180<\/td>\n6.15 White box elements <\/td>\n<\/tr>\n
181<\/td>\n6.16 White box element reference <\/td>\n<\/tr>\n
183<\/td>\n6.17 CPUs <\/td>\n<\/tr>\n
184<\/td>\n7. Design descriptions
7.1 Design <\/td>\n<\/tr>\n
186<\/td>\n7.2 Design component instances <\/td>\n<\/tr>\n
188<\/td>\n7.3 Design interconnections <\/td>\n<\/tr>\n
189<\/td>\n7.4 Active, monitored, and monitor interfaces <\/td>\n<\/tr>\n
191<\/td>\n7.5 Design ad hoc connections <\/td>\n<\/tr>\n
193<\/td>\n7.6 Design hierarchical connections <\/td>\n<\/tr>\n
196<\/td>\n8. Abstractor descriptions
8.1 Abstractor <\/td>\n<\/tr>\n
198<\/td>\n8.2 Abstractor interfaces <\/td>\n<\/tr>\n
200<\/td>\n8.3 Abstractor models <\/td>\n<\/tr>\n
202<\/td>\n8.4 Abstractor views <\/td>\n<\/tr>\n
204<\/td>\n8.5 Abstractor ports <\/td>\n<\/tr>\n
206<\/td>\n8.6 Abstractor wire ports <\/td>\n<\/tr>\n
208<\/td>\n8.7 Abstractor generators <\/td>\n<\/tr>\n
212<\/td>\n9. Generator chain descriptions
9.1 generatorChain <\/td>\n<\/tr>\n
214<\/td>\n9.2 generatorChainSelector <\/td>\n<\/tr>\n
215<\/td>\n9.3 generatorChain component selector <\/td>\n<\/tr>\n
216<\/td>\n9.4 generatorChain generator <\/td>\n<\/tr>\n
220<\/td>\n10. Design configuration descriptions
10.1 Design configuration
10.2 designConfiguration <\/td>\n<\/tr>\n
222<\/td>\n10.3 generatorChainConfiguration <\/td>\n<\/tr>\n
224<\/td>\n10.4 interconnectionConfiguration <\/td>\n<\/tr>\n
226<\/td>\n11. Addressing and data visibility
11.1 Calculating the bit address of a bit in a memory map <\/td>\n<\/tr>\n
227<\/td>\n11.2 Calculating the bus address at the slave bus interface
11.3 Address modifications of an interconnection <\/td>\n<\/tr>\n
228<\/td>\n11.4 Address modifications of a channel <\/td>\n<\/tr>\n
229<\/td>\n11.5 Addressing in the master
11.6 Visibility of bits <\/td>\n<\/tr>\n
231<\/td>\n11.7 Address translation in a bridge <\/td>\n<\/tr>\n
232<\/td>\nAnnex A (informative) Bibliography
\n <\/td>\n<\/tr>\n
234<\/td>\nAnnex B (normative) Semantic consistency rules
\n <\/td>\n<\/tr>\n
258<\/td>\nAnnex C (normative) Common elements and concepts
\n <\/td>\n<\/tr>\n
276<\/td>\nAnnex D (normative) Types
\n <\/td>\n<\/tr>\n
280<\/td>\nAnnex E (normative) Dependency XPATH
\n <\/td>\n<\/tr>\n
284<\/td>\nAnnex F (informative) External bus with an internal\/digital interface
\n <\/td>\n<\/tr>\n
286<\/td>\nAnnex G (normative) Tight generator interface
\n <\/td>\n<\/tr>\n
364<\/td>\nAnnex H (informative) Bridges and channels
\n <\/td>\n<\/tr>\n
374<\/td>\nAnnex I (informative) IEEE List of Participants <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2015<\/td>\n380<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":420671,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[697,2641],"product_tag":[],"class_list":{"0":"post-420662","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-35-240-50","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/420662","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/420671"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=420662"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=420662"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=420662"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}