{"id":421681,"date":"2024-10-20T06:37:33","date_gmt":"2024-10-20T06:37:33","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bsi-pd-iec-tr-631332017-2\/"},"modified":"2024-10-26T12:23:57","modified_gmt":"2024-10-26T12:23:57","slug":"bsi-pd-iec-tr-631332017-2","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bsi-pd-iec-tr-631332017-2\/","title":{"rendered":"BSI PD IEC\/TR 63133:2017"},"content":{"rendered":"
This Technical Report specifies a design technique of performance estimation storage element, which can monitor semiconductor ageing and characterize ageing level. The estimated ageing level can be used to improve the reliability of system.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
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2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | INTRODUCTION Figures Figure 1 \u2013 Reliability bathtub curve <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions and abbreviated terms 3.1 Terms and definitions <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | 3.2 Abbreviations <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 4 Ageing level 4.1 Overview 4.2 Ageing level characterization technique (test method) Figure 2 \u2013 Schematic of ageing level estimation technique <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | Figure 3 \u2013 A guard band and estimated ageing level <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 4.3 Architecture and operation Figure 4 \u2013 Ageing level monitoring and scan chain architecture <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 4.4 Performance estimation storage element Figure 5 \u2013 State diagram for performance estimation controller <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | Figure 6 \u2013 Modified scan cell architecture Figure 7 \u2013 Operations of shadow latch, storage element, and PERCaccording to CLK and PECLK <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 4.5 Simulation results 4.6 Experimental results Figure 8 \u2013 Simulation results for a case in which ageing occurs on a data path <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | Table 1 \u2013 Power consumption compared with prior work <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | Figure 9 \u2013 PECLKs for various delay points and their results <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Semiconductor devices. Scan based ageing level estimation for semiconductor devices<\/b><\/p>\n |