{"id":451207,"date":"2024-10-20T09:16:37","date_gmt":"2024-10-20T09:16:37","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-16603-20-402023\/"},"modified":"2024-10-26T17:17:17","modified_gmt":"2024-10-26T17:17:17","slug":"bs-en-16603-20-402023","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-16603-20-402023\/","title":{"rendered":"BS EN 16603-20-40:2023"},"content":{"rendered":"
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 1 Scope <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 2 Normative references <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 3 Terms, definitions and abbreviated terms 3.1 Terms from other standards 3.2 Terms specific to the present standard <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 3.3 Abbreviated terms <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 3.4 Conventions 3.4.1 Names of DEVICE development phases and reviews <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 3.4.2 Companies involved in the DEVICE development 3.4.3 Types of DEVICEs and requirements tailoring tag notation <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 3.5 Nomenclature <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 4 Principles 4.1 DEVICE development 4.2 Verification methods <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 5 DEVICE engineering 5.1 General requirements 5.1.1 Overview 5.1.2 Tailoring according to DEVICE type and DEVICE criticality 5.1.3 DEVICE engineering development flow <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 5.1.4 Phase Reviews 5.1.5 DEVICE Verification Control Document <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | 5.2 DEVICE Definition Phase 5.2.1 Overview 5.2.2 DEVICE Requirements Specification 5.2.3 DEVICE Development Plan <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 5.2.4 Preliminary Verification and Validation Plans 5.2.5 Preliminary DEVICE Support and Maintenance Plan 5.2.6 Feasibility and Risk Assessment <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 5.2.7 DEVICE Definition Phase Review 5.3 DEVICE Architecture Definition Phase 5.3.1 Overview 5.3.2 Architecture Definition <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 5.3.3 Updated DEVICE Verification and Validation Plans 5.3.4 DEVICE Architecture Definition Phase Review 5.4 DEVICE Design and Verification Phase 5.4.1 Overview <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 5.4.2 DEVICE Verification Plan 5.4.3 DEVICE Design and Verification <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | 5.4.4 DEVICE Database <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 5.4.5 Preliminary DEVICE Data Sheet 5.4.6 DEVICE Design and Verification Phase Review <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 5.5 DEVICE Detailed Design Phase 5.5.1 Overview 5.5.2 Netlist Generation <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | 5.5.3 Netlist verification 5.5.4 DEVICE Data Sheet update 5.5.5 DEVICE Database update <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 5.5.6 DEVICE Detailed Design Phase Review 5.6 DEVICE Layout Phase 5.6.1 Overview 5.6.2 Layout generation <\/td>\n<\/tr>\n | ||||||
41<\/td>\n | 5.6.3 Layout verification 5.6.4 DEVICE Validation Plan 5.6.5 DEVICE Database update 5.6.6 DEVICE Data Sheet update 5.6.7 Preliminary ESCC Detail Specification <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | 5.6.8 DEVICE Layout Phase Review 5.7 DEVICE Implementation Phase 5.7.1 Overview <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | 5.7.2 Production and test 5.7.3 DEVICE Database update <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | 5.7.4 DEVICE Validation Plan completion 5.7.5 DEVICE Implementation Phase Review 5.8 DEVICE Validation, Qualification and Acceptance Phase 5.8.1 Overview <\/td>\n<\/tr>\n | ||||||
45<\/td>\n | 5.8.2 DEVICE validation 5.8.3 DEVICE Support and Maintenance 5.8.4 Experience Summary Report <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 5.8.5 Final versions of application and procurement documents 5.8.6 DEVICE Validation, Qualification and Acceptance Phase Review <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 6 Pre-tailoring according to DEVICE criticality and type 6.1 DEVICE criticality categories <\/td>\n<\/tr>\n | ||||||
51<\/td>\n | 6.2 Pre-tailoring Matrix <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Space engineering. ASIC, FPGA and IP Core engineering<\/b><\/p>\n |