{"id":82581,"date":"2024-10-18T03:06:46","date_gmt":"2024-10-18T03:06:46","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-581-1978\/"},"modified":"2024-10-24T19:50:41","modified_gmt":"2024-10-24T19:50:41","slug":"ieee-581-1978","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-581-1978\/","title":{"rendered":"IEEE 581 1978"},"content":{"rendered":"
New IEEE Standard – Inactive – Withdrawn. no abstract. Withdrawn Standard. Withdrawn Date: Dec 05, 1991.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
7<\/td>\n | 1.Introduction 1.1MOSandMNOS 1.2 Description of This Standard <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | 1.3 Mechanism of MNOS Memory Transistor MNOS Transistor <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 1.4 Restrictions 2 Symbols and Definitions <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 3.References <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 4 MNOS Memory Threshold Definition and Measurement 4.1Background MOS Transistor <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | IGFET Circuit Symbols for Both Nonmemory and Memory Types <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 4.2 Threshold Voltage Test Methods Zero Current Method for Threshold Voltage Measurement <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | Plot of f\/l DS Versus V Measurement <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 4.3 Threshold Voltage Shifts Saturated Drain-Constant Current Method of Threshold Voltage Measurement Source Follower-Constant Current Method of Threshold Voltage Measurement <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 5 Writing Characteristics of MNOS Memory Transistors 5.1Background <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 5.2 Methods for Deriving Writing Characteristics Pulse Sequence to Measure Writing Characteristics Fig 10 Writing Characteristic at Constant Writing Voltage <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | Fig 11 Typical Family of Writing Characteristics Fig 12 Pulse Train for Unsaturated Writing <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 6 Retention of MNOS Memory Transistors 6.1Background Fig 13 Retention Plot <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 6.2 Methods of Measurement <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | Fig 14 Starting Condition for LC State Fig 15 Starting Condition for HC State <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | Fig 17 Zero Bias Retention Plot <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 6.3 Accelerated Retention Measurements Fig 18 Measurement of Retention at Constant Current Fig 19 Constant Drain Current Retention Plot <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | Fig 20 Constant Gate Voltage Retention Plot <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 7 Endurance of MNOS Memory Transistors 7.1Background 7.2 Measurement of Endurance Fig 21 Retention Plot Before and After Write-Erase Cycling for EAROM <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | Fig 22 Pulse Train for Write-High-Write-Low Cycling Fig 23 Presentation of Endurance Data Definition tRo at Limit = tR0\/2 <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | Fig 25 Decay Constant Versus Accumulated Write-Erase Dose for Various Nitride Thicknesses <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 7.3 Accelerated Endurance Testing 8 Basic Device Characteristics 8.1Background 8.2 Testing of Device Parameters <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | Fig 26 Reverse Drain Breakdown Walkout <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 8.3 Device Construction and Description Fig 27 Relationship of Gate Stress to Writing Characteristics <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 9 Radiation Effects on MNOS Memory Transistors 9.1Background Fig 28 Protected Source-Drain MNOS Structure Table 2 MNOS Device Description (Sample) Table 3 MNOS Process Description <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | 9.2 Measurement of Radiation Effects <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | Fig 29 MNOS RAM Writing Characteristic After Irradiation with CO 60 Gamma Fig 30 MNOS RAM Data Retention After Irradiation with CO 60 Gamma <\/td>\n<\/tr>\n | ||||||
40<\/td>\n | Fig 31 MNOS Memory Transistor Parameter Checker <\/td>\n<\/tr>\n | ||||||
41<\/td>\n | Fig 32 MNOS Test Fixture and Threshold Seeker Waveforms <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | Fig 33 Typical Flash X-Ray Timing Sequence Fig 34 Flash X-Ray Test Setup <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | 10 Alphabetical Subject Index Fig 35 Effect of High Dose Rate on Data Retention in MNOS RAM <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" IEEE Standard Definitions, Symbols, and Characterization of Metal-Nitrite-Oxide Field-Effect Transistors<\/b><\/p>\n |