This Standard specifies the electrical characteristics of low
\nvoltage differential signaling interface circuits, normally
\nimplemented in integrated circuit technology, that may be employed
\nwhen specified for the interchange of binary signals between:<\/p>\n
Data Terminal Equipment (DTE) and Data Circuit-Terminating
\nEquipment (DCE),<\/p>\n
Data Terminal Equipment (DTE) and Data Terminal Equipment
\n(DTE),<\/p>\n
or in any point-to-point, or multidrop interconnection of binary
\nsignals between equipment.<\/p>\n
The interface circuit includes a generator connected by a
\nbalanced interconnecting media to a load consisting of a
\ntermination impedance and a receiver(s). The interface
\nconfiguration is a point-to-point or multidrop interface. The
\nelectrical characteristics of the circuit are specified in terms of
\nrequired voltage, and current values obtained from direct
\nmeasurements of the generator and receiver (load) components at the
\ninterface points.<\/p>\n
The logic function of the generator and the receiver is not
\ndefined by this Standard, as it is application dependent. The
\ngenerators and receivers may be inverting, non-inverting, or may
\ninclude other digital blocks such as parallel-to-serial or
\nserial-to-parallel converters to boost the data signaling rate on
\nthe interchange circuit as required by the application.<\/p>\n
Minimum performance requirements for the balanced
\ninterconnecting media are furnished. Guidance is given in Annex A,
\nSection A.2 with respect to limitations on data signaling rate
\nimposed by the parameters of the cable length, attenuation, and
\ncrosstalk for individual installations for a typical cable media
\ninterface.<\/p>\n
It is intended that this Standard will be referenced by other
\nstandards that specify the complete interface (i.e., connector, pin
\nassignments, function) for applications where the electrical
\ncharacteristics of a low voltage differential signaling interface
\ncircuit is required. This Standard does not specify other
\ncharacteristics of the DTE-DCE interface (such as signal quality,
\nprotocol, maximum data signaling rate, bus structure, and\/or
\ntiming) essential for proper operation across the interface.<\/p>\n
When this Standard is referenced by other standards or
\nspecifications, it should be noted that certain options are
\navailable. The preparer of those standards and specifications must
\ndetermine and specify those optional features which are required
\nfor that application.<\/p>\n","protected":false},"excerpt":{"rendered":"
Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits<\/b><\/p>\n\n\n
\n Published By<\/td>\n Publication Date<\/td>\n Number of Pages<\/td>\n<\/tr>\n \n TIA<\/b><\/a><\/td>\n 2001<\/td>\n 42<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":691734,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2646],"product_tag":[],"class_list":{"0":"post-691726","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-tia","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/691726","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/691734"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=691726"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=691726"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=691726"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}